peter/spectre-meltdown-checker
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spectre-meltdown-checker
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  • 687ce1a7fa fix: load cpuid module if absent even when /dev/cpu/0/cpuid is there Stéphane Lesimple 2018-09-08 23:15:21 +0200
  • b5a631750c add SPDX GPL-3.0 license identifier Luis Ponce 2018-09-05 12:53:41 -0500
  • a827bc1d52 Add Clear Linux Distro Luis Ponce 2018-09-05 12:28:29 -0500
  • 9d460ef879 Fix tab indent Pierre Gaxatte 2018-09-04 08:56:55 +0200
  • 221b202d0d Add a batch short option for one line result Pierre Gaxatte 2018-09-04 08:37:35 +0200
  • bdfcba4dae Correct aarch64 KPTI dmesg message Stanislav Kholmanskikh 2018-08-29 05:40:52 -0700
  • dbe1c5b34c Fix a typo in check_variant3_linux() Stanislav Kholmanskikh 2018-08-28 04:35:44 -0700
  • 80e0db7cc4 fix: don't show erroneous ucode version when latest version is unknown (fixes #238) Stéphane Lesimple 2018-08-28 20:51:34 +0200
  • e8890ffac6 feat(config): support for genkernel kernel config file (#239) David Guglielmi 2018-08-28 20:24:37 +0200
  • 15d1bb2e4d
         config: support for genkernel kernel config file David Guglielmi 2018-08-21 11:14:41 +0200
  • badc00055e
         Merge 9ebb69b9c3 into b2f64e1132 Rob Gill 2018-08-18 10:12:26 +0000
  • b2f64e1132 fix README after merge Stéphane Lesimple 2018-08-18 12:09:34 +0200
  • 42a3a61f1d Slightly improved Docker configuration (#230) unrealization 2018-08-18 12:06:16 +0200
  • afb36c519d Fix typo: 'RBS filling' => 'RSB filling' (#237) Karsten Weiss 2018-08-18 12:05:17 +0200
  • 0009c0d473 fix: --batch now implies --no-color to avoid colored warnings Stéphane Lesimple 2018-08-18 12:04:18 +0200
  • 34cccad0aa Fix typo: 'RBS filling' => 'RSB filling' Karsten Weiss 2018-08-17 17:53:58 +0200
  • 9ebb69b9c3 Merge branch 'lfps' of https://github.com/rrobgill/spectre-meltdown-checker into lfps Rob Gill 2018-08-17 23:36:51 +1000
  • 587e461a88 Opcode counting heuristics for EAGERfp presence in kernels Rob Gill 2018-08-17 23:34:41 +1000
  • 6031a19582
         Merge pull request #1 from speed47/master unrealization 2018-08-16 19:24:20 +0200
  • dd67fd94d7 feat: add FLUSH_CMD MSR availability detection (part of L1TF mitigation) Stéphane Lesimple 2018-08-16 19:05:09 +0200
  • 8e11bd9468
         Merge branch 'master' into lfps Rob Gill 2018-08-17 01:51:32 +1000
  • 339ad31757 fix: add missing l1tf CPU vulnerability display in hw section Stéphane Lesimple 2018-08-16 15:19:29 +0200
  • 794c5be1d2 feat: add optional git describe support to display inter-release version numbers Stéphane Lesimple 2018-08-16 15:18:47 +0200
  • f03382b81f LazyFPState Restore / CVE-2018-3665 Rob Gill 2018-08-16 20:25:16 +1000
  • a7afc585a9 fix several incorrect ucode version numbers Stéphane Lesimple 2018-08-16 10:51:55 +0200
  • 481952e14f Added docker-compose.yml for convenience as users won't need to manually specify volumes and stuff when running through docker-compose. unrealization 2018-08-15 14:16:21 +0200
  • 314e9a5500 Listed the required volumes in the Dockerfile. unrealization 2018-08-15 14:15:52 +0200
  • fc1dffd09a feat: implement detection of latest known versions of intel microcodes Stéphane Lesimple 2018-08-15 12:53:49 +0200
  • e942616189 feat: initial support for L1TF Stéphane Lesimple 2018-08-15 11:59:23 +0200
  • 360be7b35f fix: hide arch_capabilities_msr_not_read warning under !intel v0.39 Stéphane Lesimple 2018-08-13 15:42:56 +0200
  • 5f59257826 bump to v0.39 Stéphane Lesimple 2018-08-13 15:33:03 +0200
  • 92d59cbdc1 chore: adjust some comments, add 2 missing inits Stéphane Lesimple 2018-08-11 10:31:10 +0200
  • 4747b932e7 feat: add detection of RSBA feature bit and adjust logic accordingly Stéphane Lesimple 2018-08-09 21:03:58 +0200
  • 860023a806 fix: ARCH MSR was not read correctly, preventing proper SSB_NO and RDCL_NO detection Stéphane Lesimple 2018-08-09 10:02:44 +0200
  • ab67a9221d feat: read/write msr now supports msr-tools or perl as dd fallback Stéphane Lesimple 2018-08-08 16:52:31 +0200
  • f4592bf3a8 Add Arch armv5/armv7 kernel image location (#227) 0x9fff00 2018-08-09 22:13:30 +0200
  • 98174eea46
         Add Arch armv5/armv7 kernel image location 0x9fff00 2018-08-09 21:39:51 +0200
  • be15e47671 chore: setting master to v0.38+ Stéphane Lesimple 2018-08-09 14:25:22 +0200
  • d3481d9524 Add support for the kernel being within a btrfs subvolume (#226) Nathan Parsons 2018-08-09 13:00:35 +0100
  • 4ff9ec2bcd
         Add support for the kernel being within a btrfs subvolume Nathan Parsons 2018-08-08 11:24:02 +0100
  • 21af561148 bump to v0.38 v0.38 Stéphane Lesimple 2018-08-07 10:55:50 +0200
  • cb740397f3 feat(arm32): add spectrev1 mitigation detection Stéphane Lesimple 2018-08-01 21:30:13 +0200
  • 84195689af change: default to --no-explain, use --explain to get detailed mitigation help Stéphane Lesimple 2018-08-04 16:31:41 +0200
  • b637681fa8 fix: debug output: msg inaccuracy for ARM checks Stéphane Lesimple 2018-08-01 20:40:20 +0200
  • 9316c30577 fix: armv8: models < 0xd07 are not vulnerable Stéphane Lesimple 2018-08-01 00:31:31 +0200
  • f9dd9d8cb9 add guess for archlinuxarm aarch64 kernel image on raspberry pi 3 (#222) Lily Wilson 2018-07-31 18:15:52 -0400
  • 9e044f88c7 add guess for archlinuxarm aarch64 kernel image on raspberry pi 3 Lily Wilson 2018-07-27 21:56:24 +0000
  • 0f0d103a89 fix: correctly init capabilities_ssb_no var in all cases Stéphane Lesimple 2018-07-26 10:18:14 +0200
  • b262c40541 fix: remove spurious character after an else statement Stéphane Lesimple 2018-07-25 21:55:50 +0200
  • cc2910fbbc fix: read_cpuid: don't use iflag=skip_bytes for compat with old dd versions Stéphane Lesimple 2018-07-22 20:07:44 +0200
  • 30c4a1f6d2 arm64: cavium: Add CPU Implementer Cavium (#216) manish jaggi 2018-07-22 22:36:19 +0530
  • a2bde9a8f0 arm64: cavium: Add CPU Implementer Cavium Manish Jaggi 2018-06-28 11:26:28 +0530
  • cf06636a3f fix: prometheus output: use printf for proper \n interpretation (#204) Stéphane Lesimple 2018-06-21 23:35:51 +0200
  • e9fa4fccba
         Merge 2652123fe1 into 60077c8d12 Jan 2018-06-21 21:33:11 +0000
  • 60077c8d12 fix(arm): rewrite vuln logic from latest arm statement for Cortex A8 to A76 Stéphane Lesimple 2018-06-21 23:24:18 +0200
  • 3c0ecc0c31
         Merge c1f7629587 into c181978d7c Rob Gill 2018-06-18 10:40:19 +0000
  • c1f7629587
         Whitelist non-vulnerable ARMv7 Rob Gill 2018-06-18 20:39:32 +1000
  • 66835c75f3
         Merge pull request #1 from speed47/master Rob Gill 2018-06-18 20:35:40 +1000
  • c181978d7c fix(arm): Updated arm cortex status (#209) Rob Gill 2018-06-16 20:14:39 +1000
  • 80c905bab9
         trailing tab Rob Gill 2018-06-15 07:00:36 +1000
  • e285d263d9
         Update spectre-meltdown-checker.sh Rob Gill 2018-06-15 06:59:35 +1000
  • 9a6406a9a2 chore: add docker support (#203) Jan 2018-06-14 20:25:35 +0200
  • e7cf189d85
         ARM Cortex Whitelist & Cumulative Blacklist Rob Gill 2018-06-12 22:54:20 +1000
  • 5976746072
         Update spectre-meltdown-checker.sh Rob Gill 2018-06-12 08:13:48 +1000
  • 9851133a25
         Whitelist variant4 nonvuln Arms Rob Gill 2018-06-12 08:03:37 +1000
  • ecff9b929e
         A76 vulnerable to variant 4 Rob Gill 2018-06-12 07:50:16 +1000
  • 556dd02591
         ARM Cortex A12 Vulnerable to 1&2 Rob Gill 2018-06-12 07:34:39 +1000
  • b29d42ede0
         Cortex A8 Vulnerable Rob Gill 2018-06-12 07:17:30 +1000
  • 2652123fe1 fix: line breaks in prometheus batch mode Jan Kunzmann 2018-06-08 11:52:02 +0200
  • a2df625d83 chore: add docker support Jan Kunzmann 2018-06-07 18:17:08 +0200
  • 0eb563adc6
         Merge c40b2b3195 into 5962d20ba7 Rob Gill 2018-05-27 20:40:50 +0000
  • 5962d20ba7 fix(variant4): whitelist from common.c::cpu_no_spec_store_bypass (#202) Rob Gill 2018-05-27 23:14:29 +1000
  • d5840a9f87
         remove duplicates Rob Gill 2018-05-27 19:54:25 +1000
  • 060e63d615
         amd families fix Rob Gill 2018-05-27 08:58:38 +1000
  • 2475482a98
         variant4 from common.c::cpu_no_spec_store_bypass Rob Gill 2018-05-25 21:36:29 +1000
  • 1c793775ba
         Merge pull request #5 from speed47/master Rob Gill 2018-05-25 21:29:20 +1000
  • 17a3488505 fix(help): add missing references to variants 3a & 4 (#201) Rob Gill 2018-05-25 00:35:57 +1000
  • e54e8b3e84 chore: remove warning in README, fix display indentation Stéphane Lesimple 2018-05-24 16:32:53 +0200
  • 09deb46d3e
         Add missing references to variants 3a & 4 Rob Gill 2018-05-24 21:45:28 +1000
  • 17b6e182d9
         Merge pull request #4 from speed47/master Rob Gill 2018-05-24 11:18:35 +1000
  • 39c778e3ac fix(amd): AMD families 0x15-0x17 non-arch MSRs are a valid way to control SSB Stéphane Lesimple 2018-05-23 23:08:07 +0200
  • 2cde6e4649 feat(ssbd): add detection of proper CPUID bits on AMD Stéphane Lesimple 2018-05-23 22:50:52 +0200
  • f4d51e7e53 fix(variant4): add another detection way for Red Hat kernel Stéphane Lesimple 2018-05-23 22:47:54 +0200
  • 85d46b2799 feat(variant4): add more detailed explanations Stéphane Lesimple 2018-05-23 21:08:58 +0200
  • 61e02abd0c feat(variant3a): detect up to date microcode Stéphane Lesimple 2018-05-23 21:08:08 +0200
  • 114756fab7 fix(amd): not vulnerable to variant3a Stéphane Lesimple 2018-05-23 20:38:43 +0200
  • ea75969eb7 fix(help): Update variant options in usage message (#200) Rob Gill 2018-05-22 23:54:25 +1000
  • 7e4890c12c
         Update variant options in usage message Rob Gill 2018-05-22 21:54:28 +1000
  • c40b2b3195
         Update spectre-meltdown-checker.sh Rob Gill 2018-05-22 21:11:19 +1000
  • 7451022f05
         Update spectre-meltdown-checker.sh Rob Gill 2018-05-22 20:46:49 +1000
  • e04c6b9850
         Check for obsolete dd Rob Gill 2018-05-22 20:40:57 +1000
  • ca391cbfc9 fix(variant2): correctly detect IBRS/IBPB in SLES kernels Stéphane Lesimple 2018-05-22 12:06:46 +0200
  • 68af5c5f92 feat(variant4): detect SSBD-aware kernel Stéphane Lesimple 2018-05-22 12:05:46 +0200
  • 65c123f309
         Merge pull request #3 from speed47/master Rob Gill 2018-05-22 18:14:24 +1000
  • 19be8f79eb doc: update README with some info about variant3 and variant4 Stéphane Lesimple 2018-05-22 09:43:29 +0200
  • f75cc0bb6f feat(variant4): add sysfs mitigation hint and some explanation about the vuln Stéphane Lesimple 2018-05-22 09:39:11 +0200
  • f33d65ff71 feat(variant3a): add information about microcode-sufficient mitigation Stéphane Lesimple 2018-05-22 09:38:29 +0200
  • 725eaa8bf5 feat(arm): adjust vulnerable ARM CPUs for variant3a and variant4 Stéphane Lesimple 2018-05-22 09:19:29 +0200
  • c6ee0358d1 feat(variant4): report SSB_NO CPUs as not vulnerable Stéphane Lesimple 2018-05-22 09:18:30 +0200
  • 0230ce23b1
         Merge pull request #2 from speed47/master Rob Gill 2018-05-22 14:57:29 +1000