release: sync v26.36.0913490 from source-build

built from source-build commit b4d3328cc1
 dated 2026-09-13 11:47:12 +0000

.github/workflows/autoupdate.yml

@@ -17,25 +17,107 @@ jobs:
         with:
           ref: source
       - name: Install prerequisites
-        run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iucode-tool sqlite3 unzip shfmt
+        run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iucode-tool sqlite3 unzip shfmt python3
       - name: Update microcode versions
         run: ./scripts/update_mcedb.sh
       - name: Update Intel models
         run: ./scripts/update_intel_models.sh
+      - name: Update Intel affected processors
+        run: |
+          git clone https://github.com/intel/Intel-affected-processor-list.git \
+            "$RUNNER_TEMP/Intel-affected-processor-list"
+          python3 scripts/intel-affected-processor-list/build_inteldb.py \
+            "$RUNNER_TEMP/Intel-affected-processor-list" src/db/100_inteldb.sh \
+            --base-db scripts/intel-affected-processor-list/historical_records.db
       - name: Check git diff
         id: diff
         run: |
-          echo change="$(git diff | awk '/MCEDB/ { if(V) { print V" to "$4; exit } else { V=$4 } }')" >> "$GITHUB_OUTPUT"
-          echo nbdiff="$(git diff | grep -cE -- '^\+# [AI],')" >> "$GITHUB_OUTPUT"
+          if git diff --quiet -- src/db/200_mcedb.sh src/libs/003_intel_models.sh src/db/100_inteldb.sh; then
+            echo "changed=false" >> "$GITHUB_OUTPUT"
+          else
+            echo "changed=true" >> "$GITHUB_OUTPUT"
+          fi
+          python3 - <<'PY'
+          import os
+          import re
+          import subprocess
+          from pathlib import Path
+
+          def previous(path):
+              return subprocess.check_output(['git', 'show', f'HEAD:{path}'], text=True)
+
+          def records(text, kind):
+              result = {}
+              for line in text.splitlines():
+                  if kind == 'microcode' and re.match(r'^# [AI],', line):
+                      fields = line[2:].split(',')
+                      result[tuple(fields[:3])] = tuple(fields[3:])
+                  elif kind == 'models':
+                      match = re.match(r'\s*readonly (INTEL_\w+)=(.*)', line)
+                      if match:
+                          result[match[1]] = match[2]
+                  elif kind == 'processors' and line.startswith('# 0x'):
+                      fields = line[2:].rstrip(',').split(',')
+                      qualifier = fields[1] if fields[1].startswith('H=') else ''
+                      result[(fields[0], qualifier)] = tuple(fields[2:] if qualifier else fields[1:])
+              return result
+
+          outputs = {}
+          for kind, path in (
+              ('microcode', 'src/db/200_mcedb.sh'),
+              ('models', 'src/libs/003_intel_models.sh'),
+              ('processors', 'src/db/100_inteldb.sh'),
+          ):
+              old_text = previous(path)
+              new_text = Path(path).read_text(encoding='utf-8')
+              old = records(old_text, kind)
+              new = records(new_text, kind)
+              added = len(new.keys() - old.keys())
+              removed = len(old.keys() - new.keys())
+              updated = sum(old[key] != new[key] for key in old.keys() & new.keys())
+              outputs[kind] = f'{added} added, {updated} updated, {removed} removed ({len(new)} total)'
+              if kind == 'microcode':
+                  def version(text):
+                      match = re.search(r'^# %%% MCEDB (\S+)', text, re.MULTILINE)
+                      if not match:
+                          raise ValueError('Missing MCEDB version marker')
+                      return match[1]
+                  before, after = version(old_text), version(new_text)
+                  outputs['mcedb'] = f'{before} -> {after}' if before != after else f'{after} (unchanged)'
+                  outputs['microcode_changes'] = added + updated + removed
+          outputs['intel_revision'] = subprocess.check_output(
+              ['git', '-C', os.path.join(os.environ['RUNNER_TEMP'], 'Intel-affected-processor-list'),
+               'rev-parse', 'HEAD'], text=True,
+          ).strip()
+          with open(os.environ['GITHUB_OUTPUT'], 'a', encoding='utf-8') as stream:
+              for key, value in outputs.items():
+                  print(f'{key}={value}', file=stream)
+          PY
           git diff
           cat "$GITHUB_OUTPUT"
       - name: Create Pull Request if needed
-        if: steps.diff.outputs.nbdiff != '0'
+        if: steps.diff.outputs.changed == 'true'
         uses: peter-evans/create-pull-request@v7
         with:
+          base: source
           branch: autoupdate-fwdb
-          commit-message: "update: fwdb from ${{ steps.diff.outputs.change }}, ${{ steps.diff.outputs.nbdiff }} microcode changes"
-          title: "[Auto] Update fwdb from ${{ steps.diff.outputs.change }}"
+          add-paths: |
+            src/db/200_mcedb.sh
+            src/libs/003_intel_models.sh
+            src/db/100_inteldb.sh
+          commit-message: |
+            update: CPU databases, ${{ steps.diff.outputs.microcode_changes }} microcode changes
+
+            MCEDB: ${{ steps.diff.outputs.mcedb }}
+            Microcode records: ${{ steps.diff.outputs.microcode }}
+            Intel models: ${{ steps.diff.outputs.models }}
+            Intel affected-processor profiles: ${{ steps.diff.outputs.processors }}
+            Intel CSV revision: ${{ steps.diff.outputs.intel_revision }}
+          title: "[Auto] Update CPU databases: MCEDB ${{ steps.diff.outputs.mcedb }}, ${{ steps.diff.outputs.microcode_changes }} microcode changes"
           body: |
-            Automated PR to update fwdb from ${{ steps.diff.outputs.change }}
-            Detected ${{ steps.diff.outputs.nbdiff }} microcode changes
+            Automated PR to refresh the CPU/microcode databases:
+
+            - **MCEDB version:** ${{ steps.diff.outputs.mcedb }}
+            - **Microcode records:** ${{ steps.diff.outputs.microcode }}
+            - **Intel CPU models:** ${{ steps.diff.outputs.models }}
+            - **Intel affected-processor profiles:** ${{ steps.diff.outputs.processors }}

doc/UNSUPPORTED_CVE_LIST.md

@@ -188,6 +188,18 @@ Observable timing discrepancy in some Intel processors allows an authenticated u
 
 **Why out of scope:** Like CVE-2020-24511, this is a microcode-only fix with no Linux kernel sysfs entry, no CPUID bit, no MSR, and no kernel configuration option. Detection would require a per-CPU-stepping microcode version lookup table. The vulnerability has low severity (CVSS 2.8) and practical exploitation is limited. Intel dropped microcode support for Sandy Bridge and Ivy Bridge, leaving those generations permanently vulnerable.
 
+## CVE-2021-26314 / CVE-2021-26313 — Floating-Point Value Injection (FPVI) and Speculative Code Store Bypass (SCSB)
+
+- **Bulletin:** [AMD-SB-1003](https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1003.html) (FPVI and SCSB); [AMD-SB-7050](https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7050.html) (FPVI variant, informational)
+- **Intel advisory:** [Floating Point Value Injection](https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/floating-point-value-injection.html)
+- **Research paper:** [Rage Against the Machine Clear (FPVI/SCSB) — VUSec, USENIX Security '21](https://www.vusec.net/projects/fpvi-scsb/)
+- **Affected CPUs:** All supported AMD CPU products; Intel CPUs (FPVI)
+- **CVSS:** 5.5 (Medium) for both
+
+FPVI (CVE-2021-26314) lets an attacker inject arbitrary floating-point values into the transient execution window opened by a floating-point machine clear, so that dependent operations transiently compute on attacker-influenced values that can then be inferred through a microarchitectural covert channel. SCSB (CVE-2021-26313) is the companion vulnerability where overwritten instructions may still be executed speculatively. AMD-SB-7050 documents an FPVI variant (from the "TREVEX" detection-framework paper) that can be triggered without denormal inputs; AMD considers it to fall within the existing scope of CVE-2021-26314 and assigned it no new CVE, classifying it as informational only.
+
+**Why out of scope:** The mitigation responsibility falls on individual software, not on the kernel or microcode. Both AMD and Intel recommend that software vendors analyze their code for vulnerable speculative floating-point sequences and insert an `LFENCE` to serialize execution. No microcode update, no CPUID flag, no MSR, and no kernel configuration option was issued, and there is no `/sys/devices/system/cpu/vulnerabilities/` entry for FPVI or SCSB — the kernel never added one, because the fix is not a kernel-level control. This is the same situation as [SLAM (CVE-2020-12965)](#cve-2020-12965--transient-execution-of-non-canonical-accesses-slam) and "Take A Way": the vendor's guidance is "software inserts LFENCE in its own code," leaving nothing for this tool to check. The AMD-SB-7050 variant adds nothing detectable, as it is informational and reuses the existing (software-only) FPVI guidance.
+
 ## CVE-2021-26318 — AMD Prefetch Attacks through Power and Time
 
 - **Issue:** [#412](https://github.com/speed47/spectre-meltdown-checker/issues/412)
@@ -308,6 +320,28 @@ Exploits a synchronization failure in the AMD stack engine via an undocumented M
 
 **Why out of scope:** Not a transient/speculative execution side channel. This is an architectural attack on AMD SEV-SNP confidential computing that requires hypervisor access, which is outside the threat model of this tool.
 
+## CVE-2025-52533 — AMD On-Chip Debug Interface Improper Access Control
+
+- **Advisory:** [NVD CVE-2025-52533](https://nvd.nist.gov/vuln/detail/CVE-2025-52533)
+- **Affected CPUs:** AMD (various; on-chip debug/test interface)
+- **CVSS:** 8.7 (High)
+- **CWE:** [CWE-1191 (On-Chip Debug and Test Interface With Improper Access Control)](https://cwe.mitre.org/data/definitions/1191.html)
+
+Improper access control in an on-chip debug interface could allow a privileged attacker to enable a debug interface and potentially compromise data confidentiality or integrity.
+
+**Why out of scope:** Not a transient or speculative execution vulnerability — this is an access-control flaw in a hardware debug/test interface (CWE-1191), with no side-channel or speculative execution component, and it requires a privileged attacker. There is no Linux kernel sysfs entry, no CPUID flag, and no kernel-side mitigation: the fix is delivered as platform/PSP firmware and proven via remote attestation against AMD's Key Distribution Service (KDS), with several SKUs marked "no fix planned." None of this is detectable by this tool, which inspects OS-loadable microcode revisions, CPUID/MSR bits, kernel capabilities, and sysfs.
+
+## CVE-2026-46174 — AMD Zen 2 Op Cache Improper Resource Isolation
+
+- **Bulletin:** [AMD-SB-7052](https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7052.html) (CPU OP Cache Corruption)
+- **Kernel fix:** [commit 1e23b30a80b1](https://github.com/torvalds/linux/commit/1e23b30a80b14e5764657401ee2cca030525ae8e) — `x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache`
+- **Affected CPUs:** AMD Zen 2
+- **CVSS:** 8.8 (High)
+
+Resources in the Zen 2 micro-op (op) cache can be improperly shared, causing instruction corruption that may be leveraged to execute instructions at a higher privilege level (userspace-to-kernel escalation). The Linux fix sets a bug-fix bit (bit 33) in the AMD `BP_CFG` model-specific register (`0xc001102e`) via `msr_set_bit()` in `init_amd_zen2()`, and only on bare metal (skipped when `X86_FEATURE_HYPERVISOR` is set, as the mitigation is the host's responsibility for guests).
+
+**Why out of scope:** Not a transient or speculative execution vulnerability — this is an op-cache resource-isolation bug that causes *instruction corruption* (an integrity/correctness erratum), with no side-channel or speculative data-leak component, which places it outside the vulnerability class this tool detects. It is also undetectable by this tool's standard framework: the kernel deliberately adds no `/sys/devices/system/cpu/vulnerabilities/` entry, no `X86_BUG_*` flag (so nothing in `/proc/cpuinfo`), no dmesg message, and no kernel command-line parameter. The mitigation is an unconditional inline MSR bit-set with no greppable named symbol, so it leaves no handle for no-runtime (kernel image / `System.map`) detection. The only possible check would be a live read of `BP_CFG` bit 33, which requires root and the `msr` module, works on bare metal only (guests report `N/A`), and would be a bespoke one-off outside the established CVE-detection model — the same situation as the [JCC Erratum](#no-cve--jump-conditional-code-jcc-erratum) below, but for AMD.
+
 ## No CVE — Jump Conditional Code (JCC) Erratum
 
 - **Issue:** [#329](https://github.com/speed47/spectre-meltdown-checker/issues/329)