Merge pull request #3 from speed47/master

merge
This commit is contained in:
Rob Gill 2018-05-22 18:14:24 +10:00 committed by GitHub
commit 65c123f309
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1 changed files with 18 additions and 2 deletions

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@ -297,6 +297,13 @@ is_cpu_vulnerable()
variant3=immune
_debug "is_cpu_vulnerable: RDCL_NO is set so not vuln to meltdown"
fi
if [ "$capabilities_ssb_no" = 1 ]; then
# capability bit for future Intel processor that will explicitly state
# that they're not vulnerable to Variant 4
# this var is set in check_cpu()
variant4=immune
_debug "is_cpu_vulnerable: SSB_NO is set so not vuln to variant4"
fi
elif is_amd; then
# AMD revised their statement about variant2 => vulnerable
# https://www.amd.com/en/corporate/speculative-execution
@ -358,14 +365,23 @@ is_cpu_vulnerable()
variant3a=vuln
else
_debug "checking cpu$i: this arm non vulnerable to variant3a"
[ -z "$variant3" ] && variant3a=immune
[ -z "$variant3a" ] && variant3a=immune
fi
# for variant4, only A57-72-73-75 are vulnerable
if [ "$cpuarch" = 8 ] && echo "$cpupart" | grep -Eq '^0xd0[789a]$'; then
_debug "checking cpu$i: arm A57-A72-A73-A75 vulnerable to variant4"
variant4=vuln
else
_debug "checking cpu$i: this arm non vulnerable to variant4"
[ -z "$variant4" ] && variant4=immune
fi
fi
_debug "is_cpu_vulnerable: for cpu$i and so far, we have <$variant1> <$variant2> <$variant3> <$variant3a> <$variant4>"
done
fi
# from the information we have for now, it seems that CPUs that are vulnerable to variant1 are also vulnerable to variant4
variant4=$variant1
[ -z "$variant4" ] && variant4=$variant1
_debug "is_cpu_vulnerable: temp results are <$variant1> <$variant2> <$variant3> <$variant3a> <$variant4>"
# if at least one of the cpu is vulnerable, then the system is vulnerable
[ "$variant1" = "immune" ] && variant1=1 || variant1=0