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https://github.com/speed47/spectre-meltdown-checker.git
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feat: add TSX_CTRL MSR detection in hardware info
This commit is contained in:
Stéphane Lesimple
parent
bd47275501
commit
4fc2afe1bc
@ -2319,15 +2319,15 @@ read_msr()
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return 200 # permission error
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# if rdmsr is available, use it
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elif command -v rdmsr >/dev/null 2>&1 && [ "$SMC_NO_RDMSR" != 1 ]; then
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_debug "read_msr: using rdmsr"
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_debug "read_msr: using rdmsr on $_msr"
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read_msr_value=$(rdmsr -r $_msr_dec 2>/dev/null | od -t u8 -A n)
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# or if we have perl, use it, any 5.x version will work
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elif command -v perl >/dev/null 2>&1 && [ "$SMC_NO_PERL" != 1 ]; then
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_debug "read_msr: using perl"
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_debug "read_msr: using perl on $_msr"
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read_msr_value=$(perl -e "open(M,'<','/dev/cpu/$_cpu/msr') and seek(M,$_msr_dec,0) and read(M,\$_,8) and print" | od -t u8 -A n)
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# fallback to dd if it supports skip_bytes
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elif dd if=/dev/null of=/dev/null bs=8 count=1 skip="$_msr_dec" iflag=skip_bytes 2>/dev/null; then
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_debug "read_msr: using dd"
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_debug "read_msr: using dd on $_msr"
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read_msr_value=$(dd if=/dev/cpu/"$_cpu"/msr bs=8 count=1 skip="$_msr_dec" iflag=skip_bytes 2>/dev/null | od -t u8 -A n)
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else
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_debug "read_msr: got no rdmsr, perl or recent enough dd!"
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@ -2709,22 +2709,6 @@ check_cpu()
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fi
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fi
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if is_intel; then
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_info " * TSX Asynchronous Abort"
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_info_nol " * TSX support is available: "
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read_cpuid 0x7 $EDX 11 1 1; ret=$?
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if [ $ret -eq 0 ]; then
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cpuid_rtm=1
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pstatus green YES "TSX RTM feature bit"
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elif [ $ret -eq 2 ]; then
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cpuid_rtm=-1
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pstatus yellow UNKNOWN "is cpuid kernel module available?"
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else
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cpuid_rtm=0
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pstatus yellow NO
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fi
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fi
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if is_intel; then
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_info " * Enhanced IBRS (IBRS_ALL)"
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_info_nol " * CPU indicates ARCH_CAPABILITIES MSR availability: "
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@ -2750,6 +2734,7 @@ check_cpu()
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capabilities_l1dflush_no=-1
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capabilities_ssb_no=-1
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capabilities_pschange_msc_no=-1
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capabilities_tsx_ctrl_msr=-1
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if [ "$cpuid_arch_capabilities" = -1 ]; then
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pstatus yellow UNKNOWN
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elif [ "$cpuid_arch_capabilities" != 1 ]; then
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@ -2761,6 +2746,7 @@ check_cpu()
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capabilities_l1dflush_no=0
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capabilities_ssb_no=0
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capabilities_pschange_msc_no=0
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capabilities_tsx_ctrl_msr=0
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pstatus yellow NO
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elif [ ! -e /dev/cpu/0/msr ] && [ ! -e /dev/cpuctl0 ]; then
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spec_ctrl_msr=-1
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@ -2795,7 +2781,9 @@ check_cpu()
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capabilities_l1dflush_no=0
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capabilities_ssb_no=0
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capabilities_pschange_msc_no=0
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capabilities_tsx_ctrl_msr=0
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if [ $val -eq 0 ]; then
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# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/x86/include/asm/msr-index.h#n82
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_debug "capabilities MSR is $capabilities (decimal)"
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[ $(( capabilities >> 0 & 1 )) -eq 1 ] && capabilities_rdcl_no=1
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[ $(( capabilities >> 1 & 1 )) -eq 1 ] && capabilities_ibrs_all=1
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@ -2804,6 +2792,7 @@ check_cpu()
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[ $(( capabilities >> 4 & 1 )) -eq 1 ] && capabilities_ssb_no=1
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[ $(( capabilities >> 5 & 1 )) -eq 1 ] && capabilities_mds_no=1
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[ $(( capabilities >> 6 & 1 )) -eq 1 ] && capabilities_pschange_msc_no=1
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[ $(( capabilities >> 7 & 1 )) -eq 1 ] && capabilities_tsx_ctrl_msr=1
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[ $(( capabilities >> 8 & 1 )) -eq 1 ] && capabilities_taa_no=1
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_debug "capabilities says rdcl_no=$capabilities_rdcl_no ibrs_all=$capabilities_ibrs_all rsba=$capabilities_rsba l1dflush_no=$capabilities_l1dflush_no ssb_no=$capabilities_ssb_no mds_no=$capabilities_mds_no taa_no=$capabilities_taa_no pschange_msc_no=$capabilities_pschange_msc_no"
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if [ "$capabilities_ibrs_all" = 1 ]; then
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@ -2888,6 +2877,58 @@ check_cpu()
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else
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pstatus yellow NO
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fi
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_info_nol " * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): "
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if [ "$capabilities_tsx_ctrl_msr" = -1 ]; then
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pstatus yellow UNKNOWN
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elif [ "$capabilities_tsx_ctrl_msr" = 1 ]; then
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pstatus green YES
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else
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pstatus yellow NO
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fi
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if [ "$capabilities_tsx_ctrl_msr" = 1 ]; then
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read_msr 0x122 0; ret=$?
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if [ "$ret" = 0 ]; then
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tsx_ctrl_msr=$read_msr_value
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tsx_ctrl_msr_rtm_disable=$(( tsx_ctrl_msr >> 0 & 1 ))
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tsx_ctrl_msr_cpuid_clear=$(( tsx_ctrl_msr >> 1 & 1 ))
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fi
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_info_nol " * TSX_CTRL MSR indicates TSX RTM is disabled: "
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if [ "$tsx_ctrl_msr_rtm_disable" = 1 ]; then
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pstatus blue YES
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elif [ "$tsx_ctrl_msr_rtm_disable" = 0 ]; then
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pstatus blue NO
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else
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pstatus yellow UNKNOWN "couldn't read MSR"
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fi
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_info_nol " * TSX_CTRL MSR indicates TSX CPUID bit is cleared: "
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if [ "$tsx_ctrl_msr_cpuid_clear" = 1 ]; then
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pstatus blue YES
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elif [ "$tsx_ctrl_msr_cpuid_clear" = 0 ]; then
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pstatus blue NO
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else
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pstatus yellow UNKNOWN "couldn't read MSR"
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fi
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fi
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fi
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_info_nol " * CPU supports Transactional Synchronization Extensions (TSX): "
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ret=1
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cpuid_rtm=0
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if is_intel; then
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read_cpuid 0x7 $EDX 11 1 1; ret=$?
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fi
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if [ $ret -eq 0 ]; then
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cpuid_rtm=1
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pstatus green YES
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elif [ $ret -eq 2 ]; then
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cpuid_rtm=-1
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pstatus yellow UNKNOWN "is cpuid kernel module available?"
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else
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pstatus yellow NO
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fi
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_info_nol " * CPU supports Software Guard Extensions (SGX): "
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@ -4285,7 +4326,8 @@ check_CVE_2018_3639_bsd()
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pvulnstatus $cve OK "SSBD mitigates the vulnerability"
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elif [ -n "$cpuid_ssbd" ]; then
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if [ "$kernel_ssb" = 1 ]; then
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pvulnstatus $cve VULN "you need to enable ssbd through sysctl to mitigate the vulnerability"
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pvulnstatus $cve VULN "you need to enable SSBD through sysctl to mitigate the vulnerability"
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explain "To enable SSBD right now, you can run \`sysctl hw.spec_store_bypass_disable=2'. To make this change persistent across reboots, you can add 'sysctl hw.spec_store_bypass_disable=2' to /etc/sysctl.conf."
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else
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pvulnstatus $cve VULN "your kernel needs to be updated"
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fi
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@ -4804,6 +4846,7 @@ check_mds_bsd()
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fi
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else
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pvulnstatus "$cve" VULN "Your microcode and kernel are both up to date for this mitigation, but the mitigation is not active"
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explain "To enable mitigation, run \`sysctl hw.mds_disable=1'. To make this change persistent across reboots, you can add 'hw.mds_disable=1' to /etc/sysctl.conf."
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fi
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else
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pvulnstatus "$cve" OK "Your microcode and kernel are both up to date for this mitigation"
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