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Author SHA1 Message Date
github-actions[bot] 1ce22924f3 update: fwdb from v350+i20260512+1cce to v351+i20260512+1cce, 9 microcode changes
built from commit 2bd3957480
 dated 2026-06-15 11:36:12 +0000
 by speed47 (218502+speed47@users.noreply.github.com)
2026-07-03 20:00:44 +00:00
github-actions[bot] 1db12cd347 update: fwdb from v349+i20260512+1cce to v350+i20260512+1cce, 8 microcode changes (#578)
built from commit 44ba92635f
 dated 2026-06-03 14:07:02 +0200
 by github-actions[bot] (41898282+github-actions[bot]@users.noreply.github.com)

 Co-authored-by: speed47 <218502+speed47@users.noreply.github.com>
2026-06-03 12:08:36 +00:00
github-actions[bot] c107f2b2ea fix: arm64: collapse per-core CPU info lists to a single line (#576)
built from commit 7d9345a32f
 dated 2026-06-02 17:21:31 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Store the per-core implementer/part/arch/variant/revision lists
space-separated (no embedded newlines, which also cleans up JSON and
prometheus output) and dedup them for the human-readable display, so
homogeneous systems show e.g. "0x41" instead of repeating it per core.
2026-06-02 19:30:28 +02:00
Stéphane Lesimple c277a7a443 Merge remote-tracking branch 'origin/master' into source-build 2026-06-02 19:30:19 +02:00
Stéphane Lesimple 26cf31b282 Merge source-build for v26.36.0601873 (#575)
* chore: add stalebot in dryrun

 built from commit afadf53f7f
 dated 2026-04-02 13:13:19 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* Merge branch 'test' into source

 built from commit 952fe6a87f
 dated 2026-04-02 18:40:05 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* Merge pull request #530 from speed47/test

 built from commit d3c0f1a24d
 dated 2026-04-02 16:49:41 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 chore: workflows revamp

* Merge pull request #532 from speed47/test

 built from commit 6fac2d8ff1
 dated 2026-04-02 21:32:39 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Retbleed / Downfall overhald / doc updates

* enh: add known fixed ucode versions for CVE-2023-23583 (Reptar) and CVE-2024-45332 (BPI)

 built from commit cccb3c0081
 dated 2026-04-04 17:50:04 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* fix: add rebleet to --variant

 built from commit 7a7408d124
 dated 2026-04-04 18:17:35 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* Merge pull request #566 from speed47/test

 built from commit 3e2b6cc734
 dated 2026-04-20 11:02:38 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Prepare release v26.33.0420xxx

* Merge pull request #571 from speed47/test

 built from commit 0045d237fa
 dated 2026-06-01 20:44:44 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Prepare next release

* update: fwdb from v349+i20260227+615b to v349+i20260512+1cce, 19 microcode changes

 built from commit 645a79846b
 dated 2026-06-01 20:56:45 +0000
 by github-actions[bot] (41898282+github-actions[bot]@users.noreply.github.com)

---------

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2026-06-02 16:57:51 +00:00
github-actions[bot] 68116d87fd update: fwdb from v349+i20260227+615b to v349+i20260512+1cce, 19 microcode changes
built from commit 645a79846b
 dated 2026-06-01 20:56:45 +0000
 by github-actions[bot] (41898282+github-actions[bot]@users.noreply.github.com)
2026-06-01 20:58:15 +00:00
Stéphane Lesimple 3f4801e6a7 autoupdate workflow: add missing pkg 2026-06-01 20:55:08 +00:00
Stéphane Lesimple 9a3688b6fd chore: use scripts in autoupdate workflow (#572) 2026-06-01 20:52:54 +00:00
github-actions[bot] c060a2d2c9 Merge pull request #571 from speed47/test
built from commit 0045d237fa
 dated 2026-06-01 20:44:44 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Prepare next release
2026-06-01 20:46:12 +00:00
Stéphane Lesimple 0c89d162a3 chore: fix autoupdate workflow 2026-05-31 14:50:31 +02:00
林博仁 Buo-ren Lin 02fa416bab doc: readme: correct markdown indentation for unordered list items (#569)
Signed-off-by: 林博仁(Buo-ren Lin) <buo.ren.lin@gmail.com>
2026-04-20 16:02:47 +00:00
Stéphane Lesimple 1c067add59 release v26.33.0420460 (#567) 2026-04-20 15:18:11 +00:00
github-actions[bot] fe0d3f49f4 Merge pull request #566 from speed47/test
built from commit 3e2b6cc734
 dated 2026-04-20 11:02:38 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Prepare release v26.33.0420xxx
2026-04-20 11:04:05 +00:00
Stéphane Lesimple 00bb4a951c workflow: expose reconsider_age_days input + env var 2026-04-19 14:46:56 +02:00
Stéphane Lesimple 43d5b77885 chore: workflow: add manual model + window_hours inputs, add reconsider 2026-04-19 12:55:03 +02:00
Stéphane Lesimple 78a6e4a418 chore: move cron vuln-watch workflow script files to their own branch 2026-04-19 11:14:21 +02:00
Stéphane Lesimple 5af1a9fec9 chore: workflow: add scan id 2026-04-18 16:23:47 +02:00
Stéphane Lesimple b93027640f chore: vuln workflow: use opus, no persist creds, conditional upload 2026-04-18 16:19:10 +02:00
Stéphane Lesimple 5c27284119 chore: workflow: save logs 2026-04-18 16:05:15 +02:00
Stéphane Lesimple f2e5999fc0 chore: explicit prompt for workflow 2026-04-18 15:41:03 +02:00
Stéphane Lesimple 25f20b8860 chore: fix workflow perms (#558) 2026-04-18 15:29:54 +02:00
Stéphane Lesimple 77e3dbd6b2 add scheduled vuln research (#557) 2026-04-18 15:14:13 +02:00
Stéphane Lesimple 8a6f9d5d63 Implement ITS/VMScape/BTI and misc enhancements (#539)
7a7408d fix: add rebleet to --variant
cccb3c0 enh: add known fixed ucode versions for CVE-2023-23583 (Reptar) and CVE-2024-45332 (BPI)
090f109 doc: add CVE-2023-31315 (SinkClose) to the unsupported list, add categories
5dc9c3c chore: reorder CVE list in README.md
a00fab1 feat: implement CVE-2025-40300 (VMScape) and CVE-2024-45332 (BTI)
e0b818f chore: stalebot: disable dryrun by default
4af1155 feat: implement CVE-2024-28956 (ITS, Indirect Target Selection) vulnerability and mitigation detection
dfed6f3 doc: add note about more unsupported CVEs
1652977 add a generated version of src/libs/003_intel_models.sh
a089ae8 fix: sys_interface_check() must set the caller's $msg var (closes #533)
cc6bbaa chore: don't include src/ generated files in build
2717b0a doc: CVE-2020-12965 unsupported (#478)
2026-04-04 18:38:49 +02:00
Stéphane Lesimple 73b67b4a80 Merge branch 'master' into source-build 2026-04-04 16:25:35 +00:00
github-actions[bot] ea6b8efd18 fix: add rebleet to --variant
built from commit 7a7408d124
 dated 2026-04-04 18:17:35 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-04 16:23:18 +00:00
github-actions[bot] 24d92540a7 enh: add known fixed ucode versions for CVE-2023-23583 (Reptar) and CVE-2024-45332 (BPI)
built from commit cccb3c0081
 dated 2026-04-04 17:50:04 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-04 16:08:25 +00:00
Stéphane Lesimple f2d871acff fix: spurious local keyword broke sysfs based detection (#533) (#534)
The $msg var assigned in sys_interface_check() must not be
local to the func, but must capture and modify the callers'
own local $msg var
2026-04-03 01:31:58 +02:00
github-actions[bot] 553a9ec60f Merge pull request #532 from speed47/test
built from commit 6fac2d8ff1
 dated 2026-04-02 21:32:39 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 Retbleed / Downfall overhald / doc updates
2026-04-02 21:33:46 +00:00
Stéphane Lesimple 83ebe2f75f chore: update workflows (#531)
* chore: add stalebot in dryrun

 built from commit afadf53f7f
 dated 2026-04-02 13:13:19 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* Merge branch 'test' into source

 built from commit 952fe6a87f
 dated 2026-04-02 18:40:05 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)

* Merge pull request #530 from speed47/test

 built from commit d3c0f1a24d
 dated 2026-04-02 16:49:41 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 chore: workflows revamp

---------

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2026-04-02 18:53:44 +02:00
Stéphane Lesimple 75ad60f42a Merge branch 'master' into source-build 2026-04-02 16:53:03 +00:00
github-actions[bot] 931c955765 Merge pull request #530 from speed47/test
built from commit d3c0f1a24d
 dated 2026-04-02 16:49:41 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)

 chore: workflows revamp
2026-04-02 16:50:52 +00:00
github-actions[bot] c5ef0c488a Merge branch 'test' into source
built from commit 952fe6a87f
 dated 2026-04-02 18:40:05 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-02 16:41:33 +00:00
github-actions[bot] a05f8aab34 chore: add stalebot in dryrun
built from commit afadf53f7f
 dated 2026-04-02 13:13:19 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-02 11:34:30 +00:00
github-actions[bot] 99301d1cbb chore: add stalebot in dryrun
built from commit afadf53f7f
 dated 2026-04-02 13:13:19 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-02 13:33:36 +02:00
github-actions[bot] f9c3d19f72 enh: CVE-2017-5715; check for unprivileged eBPF for paranoid mode
built from commit e5c6d2d905
 dated 2026-04-01 20:37:54 +0000
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-01 21:30:51 +00:00
github-actions[bot] 8389d9593c chore: prepare for dev-build renaming to test-build
built from commit 9497abbee2723cedc561b6b785fe01fbe965ec1c
 dated 2026-03-31 19:34:52 +0200
 by Stéphane Lesimple (speed47_github@speed47.net)
2026-04-01 21:30:51 +00:00
Stéphane Lesimple 3a822fdcf2 chore: master: remove obsolete workflow 2026-03-31 19:53:57 +02:00
2 changed files with 12 additions and 33 deletions
-23
View File
@@ -188,18 +188,6 @@ Observable timing discrepancy in some Intel processors allows an authenticated u
**Why out of scope:** Like CVE-2020-24511, this is a microcode-only fix with no Linux kernel sysfs entry, no CPUID bit, no MSR, and no kernel configuration option. Detection would require a per-CPU-stepping microcode version lookup table. The vulnerability has low severity (CVSS 2.8) and practical exploitation is limited. Intel dropped microcode support for Sandy Bridge and Ivy Bridge, leaving those generations permanently vulnerable. **Why out of scope:** Like CVE-2020-24511, this is a microcode-only fix with no Linux kernel sysfs entry, no CPUID bit, no MSR, and no kernel configuration option. Detection would require a per-CPU-stepping microcode version lookup table. The vulnerability has low severity (CVSS 2.8) and practical exploitation is limited. Intel dropped microcode support for Sandy Bridge and Ivy Bridge, leaving those generations permanently vulnerable.
## CVE-2021-26314 / CVE-2021-26313 — Floating-Point Value Injection (FPVI) and Speculative Code Store Bypass (SCSB)
- **Bulletin:** [AMD-SB-1003](https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1003.html) (FPVI and SCSB); [AMD-SB-7050](https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7050.html) (FPVI variant, informational)
- **Intel advisory:** [Floating Point Value Injection](https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/floating-point-value-injection.html)
- **Research paper:** [Rage Against the Machine Clear (FPVI/SCSB) — VUSec, USENIX Security '21](https://www.vusec.net/projects/fpvi-scsb/)
- **Affected CPUs:** All supported AMD CPU products; Intel CPUs (FPVI)
- **CVSS:** 5.5 (Medium) for both
FPVI (CVE-2021-26314) lets an attacker inject arbitrary floating-point values into the transient execution window opened by a floating-point machine clear, so that dependent operations transiently compute on attacker-influenced values that can then be inferred through a microarchitectural covert channel. SCSB (CVE-2021-26313) is the companion vulnerability where overwritten instructions may still be executed speculatively. AMD-SB-7050 documents an FPVI variant (from the "TREVEX" detection-framework paper) that can be triggered without denormal inputs; AMD considers it to fall within the existing scope of CVE-2021-26314 and assigned it no new CVE, classifying it as informational only.
**Why out of scope:** The mitigation responsibility falls on individual software, not on the kernel or microcode. Both AMD and Intel recommend that software vendors analyze their code for vulnerable speculative floating-point sequences and insert an `LFENCE` to serialize execution. No microcode update, no CPUID flag, no MSR, and no kernel configuration option was issued, and there is no `/sys/devices/system/cpu/vulnerabilities/` entry for FPVI or SCSB — the kernel never added one, because the fix is not a kernel-level control. This is the same situation as [SLAM (CVE-2020-12965)](#cve-2020-12965--transient-execution-of-non-canonical-accesses-slam) and "Take A Way": the vendor's guidance is "software inserts LFENCE in its own code," leaving nothing for this tool to check. The AMD-SB-7050 variant adds nothing detectable, as it is informational and reuses the existing (software-only) FPVI guidance.
## CVE-2021-26318 — AMD Prefetch Attacks through Power and Time ## CVE-2021-26318 — AMD Prefetch Attacks through Power and Time
- **Issue:** [#412](https://github.com/speed47/spectre-meltdown-checker/issues/412) - **Issue:** [#412](https://github.com/speed47/spectre-meltdown-checker/issues/412)
@@ -320,17 +308,6 @@ Exploits a synchronization failure in the AMD stack engine via an undocumented M
**Why out of scope:** Not a transient/speculative execution side channel. This is an architectural attack on AMD SEV-SNP confidential computing that requires hypervisor access, which is outside the threat model of this tool. **Why out of scope:** Not a transient/speculative execution side channel. This is an architectural attack on AMD SEV-SNP confidential computing that requires hypervisor access, which is outside the threat model of this tool.
## CVE-2025-52533 — AMD On-Chip Debug Interface Improper Access Control
- **Advisory:** [NVD CVE-2025-52533](https://nvd.nist.gov/vuln/detail/CVE-2025-52533)
- **Affected CPUs:** AMD (various; on-chip debug/test interface)
- **CVSS:** 8.7 (High)
- **CWE:** [CWE-1191 (On-Chip Debug and Test Interface With Improper Access Control)](https://cwe.mitre.org/data/definitions/1191.html)
Improper access control in an on-chip debug interface could allow a privileged attacker to enable a debug interface and potentially compromise data confidentiality or integrity.
**Why out of scope:** Not a transient or speculative execution vulnerability — this is an access-control flaw in a hardware debug/test interface (CWE-1191), with no side-channel or speculative execution component, and it requires a privileged attacker. There is no Linux kernel sysfs entry, no CPUID flag, and no kernel-side mitigation: the fix is delivered as platform/PSP firmware and proven via remote attestation against AMD's Key Distribution Service (KDS), with several SKUs marked "no fix planned." None of this is detectable by this tool, which inspects OS-loadable microcode revisions, CPUID/MSR bits, kernel capabilities, and sysfs.
## No CVE — Jump Conditional Code (JCC) Erratum ## No CVE — Jump Conditional Code (JCC) Erratum
- **Issue:** [#329](https://github.com/speed47/spectre-meltdown-checker/issues/329) - **Issue:** [#329](https://github.com/speed47/spectre-meltdown-checker/issues/329)
+12 -10
View File
@@ -13,7 +13,7 @@
# #
# Stephane Lesimple # Stephane Lesimple
# #
VERSION='26.36.0606454' VERSION='26.36.0703833'
# --- Common paths and basedirs --- # --- Common paths and basedirs ---
readonly VULN_SYSFS_BASE="/sys/devices/system/cpu/vulnerabilities" readonly VULN_SYSFS_BASE="/sys/devices/system/cpu/vulnerabilities"
@@ -381,6 +381,7 @@ fi
readonly INTEL_FAM6_ARROWLAKE_U=$((0xB5)) readonly INTEL_FAM6_ARROWLAKE_U=$((0xB5))
readonly INTEL_FAM6_LUNARLAKE_M=$((0xBD)) # /* Lion Cove / Skymont */ readonly INTEL_FAM6_LUNARLAKE_M=$((0xBD)) # /* Lion Cove / Skymont */
readonly INTEL_FAM6_PANTHERLAKE_L=$((0xCC)) # /* Cougar Cove / Darkmont */ readonly INTEL_FAM6_PANTHERLAKE_L=$((0xCC)) # /* Cougar Cove / Darkmont */
readonly INTEL_FAM6_PANTHERLAKE_R=$((0xE5)) # /* Cougar Cove / Darkmont */
readonly INTEL_FAM6_WILDCATLAKE_L=$((0xD5)) readonly INTEL_FAM6_WILDCATLAKE_L=$((0xD5))
readonly INTEL_FAM18_NOVALAKE=$((0x01)) # /* Coyote Cove / Arctic Wolf */ readonly INTEL_FAM18_NOVALAKE=$((0x01)) # /* Coyote Cove / Arctic Wolf */
readonly INTEL_FAM18_NOVALAKE_L=$((0x03)) # /* Coyote Cove / Arctic Wolf */ readonly INTEL_FAM18_NOVALAKE_L=$((0x03)) # /* Coyote Cove / Arctic Wolf */
@@ -13133,7 +13134,7 @@ exit 0 # ok
# with X being either I for Intel, or A for AMD # with X being either I for Intel, or A for AMD
# When the date is unknown it defaults to 20000101 # When the date is unknown it defaults to 20000101
# %%% MCEDB v350+i20260512+1cce # %%% MCEDB v351+i20260512+1cce
# I,0x00000611,0xFF,0x00000B27,19961218 # I,0x00000611,0xFF,0x00000B27,19961218
# I,0x00000612,0xFF,0x000000C6,19961210 # I,0x00000612,0xFF,0x000000C6,19961210
# I,0x00000616,0xFF,0x000000C6,19961210 # I,0x00000616,0xFF,0x000000C6,19961210
@@ -13582,10 +13583,11 @@ exit 0 # ok
# I,0x000C06C3,0x90,0x0000011B,20260324 # I,0x000C06C3,0x90,0x0000011B,20260324
# I,0x000C06F1,0x87,0x210002E0,20251217 # I,0x000C06F1,0x87,0x210002E0,20251217
# I,0x000C06F2,0x87,0x210002E0,20251217 # I,0x000C06F2,0x87,0x210002E0,20251217
# I,0x000D0650,0xFF,0x00000008,20260208 # I,0x000D0650,0xFF,0x00000009,20260309
# I,0x000D0651,0xFF,0x00000008,20260208 # I,0x000D0651,0xFF,0x00000009,20260309
# I,0x000D0670,0xFF,0x00000137,20260218 # I,0x000D0670,0xFF,0x00000137,20260218
# I,0x000D06D0,0xFF,0x80000370,20250917 # I,0x000D06D0,0xFF,0x80000370,20250917
# I,0x000D06D1,0xFF,0x01000120,20260325
# I,0x00FF0671,0xFF,0x0000010E,20220907 # I,0x00FF0671,0xFF,0x0000010E,20220907
# I,0x00FF0672,0xFF,0x0000000D,20210816 # I,0x00FF0672,0xFF,0x0000000D,20210816
# I,0x00FF0675,0xFF,0x0000000D,20210816 # I,0x00FF0675,0xFF,0x0000000D,20210816
@@ -13687,8 +13689,8 @@ exit 0 # ok
# A,0x008A0F00,0xFF,0x08A0000B,20241125 # A,0x008A0F00,0xFF,0x08A0000B,20241125
# A,0x00A00F00,0xFF,0x0A000033,20200413 # A,0x00A00F00,0xFF,0x0A000033,20200413
# A,0x00A00F10,0xFF,0x0A00107A,20240226 # A,0x00A00F10,0xFF,0x0A00107A,20240226
# A,0x00A00F11,0xFF,0x0A0011DE,20250418 # A,0x00A00F11,0xFF,0x0A0011DF,20260312
# A,0x00A00F12,0xFF,0x0A001247,20250327 # A,0x00A00F12,0xFF,0x0A00124B,20260305
# A,0x00A00F80,0xFF,0x0A008005,20230707 # A,0x00A00F80,0xFF,0x0A008005,20230707
# A,0x00A00F82,0xFF,0x0A00820F,20241111 # A,0x00A00F82,0xFF,0x0A00820F,20241111
# A,0x00A10F00,0xFF,0x0A10004B,20220309 # A,0x00A10F00,0xFF,0x0A10004B,20220309
@@ -13734,8 +13736,8 @@ exit 0 # ok
# A,0x00B10F10,0xFF,0x0B101059,20251105 # A,0x00B10F10,0xFF,0x0B101059,20251105
# A,0x00B20F40,0xFF,0x0B204037,20251019 # A,0x00B20F40,0xFF,0x0B204037,20251019
# A,0x00B40F00,0xFF,0x0B400034,20240318 # A,0x00B40F00,0xFF,0x0B400034,20240318
# A,0x00B40F40,0xFF,0x0B404035,20251020 # A,0x00B40F40,0xFF,0x0B404038,20260408
# A,0x00B40F41,0xFF,0x0B404108,20251020 # A,0x00B40F41,0xFF,0x0B40410B,20260408
# A,0x00B60F00,0xFF,0x0B600037,20251019 # A,0x00B60F00,0xFF,0x0B60003C,20260401
# A,0x00B60F80,0xFF,0x0B608038,20251019 # A,0x00B60F80,0xFF,0x0B60803C,20260401
# A,0x00B70F00,0xFF,0x0B700037,20251019 # A,0x00B70F00,0xFF,0x0B700037,20251019