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fix: add a missing pstatus to CVE-2023-20588 check

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This commit is contained in:
Stéphane Lesimple
2026-04-08 21:42:19 +02:00
parent be0f2d20d2
commit f0fb59310e
2 changed files with 40 additions and 1 deletions
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31
src/vulns/CVE-2018-3615.sh.rej Normal file
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@@ -0,0 +1,31 @@
--- src/vulns/CVE-2018-3615.sh
+++ src/vulns/CVE-2018-3615.sh
@@ -8,15 +8,10 @@ check_CVE_2018_3615() {
pr_info "\033[1;34m$cve aka '$(cve2name "$cve")'\033[0m"
pr_info_nol "* CPU microcode mitigates the vulnerability: "
- if { [ "$cap_flush_cmd" = 1 ] || { [ "$g_msr_locked_down" = 1 ] && [ "$cap_l1df" = 1 ]; }; } && [ "$cap_sgx" = 1 ]; then
- # no easy way to detect a fixed SGX but we know that
- # microcodes that have the FLUSH_CMD MSR also have the
- # fixed SGX (for CPUs that support it), because Intel
- # delivered fixed microcodes for both issues at the same time
- #
- # if the system we're running on is locked down (no way to write MSRs),
- # make the assumption that if the L1D flush CPUID bit is set, probably
- # that FLUSH_CMD MSR is here too
+ if [ "$cap_l1df" = 1 ] && [ "$cap_sgx" = 1 ]; then
+ # the L1D flush CPUID bit indicates that the microcode supports L1D flushing,
+ # and microcodes that have this also have the fixed SGX (for CPUs that support it),
+ # because Intel delivered fixed microcodes for both issues at the same time
pstatus green YES
elif [ "$cap_sgx" = 1 ]; then
pstatus red NO
@@ -27,7 +22,7 @@ check_CVE_2018_3615() {
if ! is_cpu_affected "$cve"; then
# override status & msg in case CPU is not vulnerable after all
pvulnstatus "$cve" OK "your CPU vendor reported your CPU model as not affected"
- elif [ "$cap_flush_cmd" = 1 ] || { [ "$g_msr_locked_down" = 1 ] && [ "$cap_l1df" = 1 ]; }; then
+ elif [ "$cap_l1df" = 1 ]; then
pvulnstatus "$cve" OK "your CPU microcode mitigates the vulnerability"
else
pvulnstatus "$cve" VULN "your CPU supports SGX and the microcode is not up to date"