From eafea0d1dfdfce2dfe70fcaa00d19ddaefa9a4d4 Mon Sep 17 00:00:00 2001
From: speed47 <218502+speed47@users.noreply.github.com>
Date: Sat, 26 Sep 2026 09:43:51 +0000
Subject: [PATCH] update: CPU databases, 1 microcode changes

MCEDB: v352+i20260812+16e5 -> v352+i20260925+3c73
Microcode records: 0 added, 1 updated, 0 removed (607 total)
Intel models: 0 added, 0 updated, 0 removed (98 total)
Intel affected-processor profiles: 0 added, 0 updated, 0 removed (124 total)
Intel CSV revision: 3bc9bd4f7c0286eb2c20dca719742ca0fbde88c5
---
 src/db/200_mcedb.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/db/200_mcedb.sh b/src/db/200_mcedb.sh
index f2c9e14..3472f75 100644
--- a/src/db/200_mcedb.sh
+++ b/src/db/200_mcedb.sh
@@ -8,7 +8,7 @@
 # with X being either I for Intel, or A for AMD
 # When the date is unknown it defaults to 20000101
 
-# %%% MCEDB v352+i20260812+16e5
+# %%% MCEDB v352+i20260925+3c73
 # I,0x00000611,0xFF,0x00000B27,19961218
 # I,0x00000612,0xFF,0x000000C6,19961210
 # I,0x00000616,0xFF,0x000000C6,19961210
@@ -421,7 +421,7 @@
 # I,0x000A0680,0xFF,0x80000002,20200121
 # I,0x000A06A1,0xFF,0x00000017,20230518
 # I,0x000A06A2,0xFF,0x00000011,20230627
-# I,0x000A06A4,0xE6,0x00000028,20250924
+# I,0x000A06A4,0xE6,0x0000002B,20260903
 # I,0x000A06C0,0xFF,0x00000013,20230901
 # I,0x000A06C1,0xFF,0x00000005,20231201
 # I,0x000A06D0,0xFF,0x10000680,20240818