diff --git a/scripts/intel-affected-processor-list/.gitignore b/scripts/intel-affected-processor-list/.gitignore new file mode 100644 index 0000000..c18dd8d --- /dev/null +++ b/scripts/intel-affected-processor-list/.gitignore @@ -0,0 +1 @@ +__pycache__/ diff --git a/scripts/intel-affected-processor-list/README.md b/scripts/intel-affected-processor-list/README.md new file mode 100644 index 0000000..42e46f6 --- /dev/null +++ b/scripts/intel-affected-processor-list/README.md @@ -0,0 +1,73 @@ +# Intel affected processor database tools + +These maintainer tools generate the checker's INTELDB data using Python 3 +(standard library only) and Git. Python is not a runtime checker dependency. + +## Files + +- `parse_inteldb_csv.py`: CSV parsing, status normalization, combined CVE + expansion, duplicate-column naming, and worst-case merging. +- `build_inteldb.py`: database reading and historical merge logic +- `header.txt`: database format and status legend included by `build_inteldb.py`. +- `historical_records.db`: baseline database retaining legacy processor records + absent from Intel's CSV history. +- `test_inteldb.py`: regression checks for the database tools. +- `README.md`: usage and maintenance documentation for these tools. + +## Parse one CSV + +Run from this project's root: + +```sh +python3 scripts/intel-affected-processor-list/parse_inteldb_csv.py \ + /path/to/Intel-affected-processor-list/Intel_affected_processor_list.csv \ + /tmp/inteldb-current.db +``` + +Columns are found by header name. The hybrid column contains +`CPUID.0x7.EDX[15]=0` or `=1`, optionally followed by +`CPUID.0x1A.EAX[31:24]=20` or `=40` (hexadecimal core types). +Explicit hybrid qualifiers are retained even for a single row/profile. +`NA`, `N/A`, and empty cells are unqualified; only CSV versions **without** +the column use the original codename inference. + +Output uses the checker's existing `CPUID,H=0/1` lookup granularity. Core-type +and segment differences sharing a CPUID/hybrid key are worst-case merged; +the output does not add a core-type-specific runtime lookup. Unrecognized +hybrid expressions fail rather than silently producing unqualified entries. + +## Build from history + +Use a full clone to retain CPUs that Intel removed from later lists: + +```sh +git clone https://github.com/intel/Intel-affected-processor-list.git \ + /tmp/Intel-affected-processor-list +python3 scripts/intel-affected-processor-list/build_inteldb.py \ + /tmp/Intel-affected-processor-list /tmp/inteldb.db \ + --base-db scripts/intel-affected-processor-list/historical_records.db +``` + +- `--ref COMMIT` pins the source revision (default: the clone's `HEAD`). The + resolved commit is recorded in the output. Fetch updates in the clone before + building when needed. +- History is processed oldest-first in Git topological order, with the selected + tip processed last. This fixes the original pipeline's commit-hash glob order. +- A newer snapshot replaces **all profiles for each CPUID it contains**, + including obsolete hybrid qualifiers/unqualified fallbacks. CPUs absent + from that snapshot keep their previous data. As in the original pipeline, + replacement is per processor profile, not a union of historical CVE columns. +- `--base-db` seeds legacy entries (including XLSX-only CPUs) absent from the + entire CSV history. CSV history supersedes baseline data for CPUs it covers. +- Output is generated only after all input snapshots parse successfully. + +Both commands write to stdout if the output filename is omitted, and send +diagnostics to stderr. Review generated entries before integrating them into +`src/db/100_inteldb.sh`; that file also carries format documentation and build +boundary markers. + +## Regression checks + +```sh +python3 -m unittest discover -s scripts/intel-affected-processor-list -p 'test_*.py' +``` diff --git a/scripts/intel-affected-processor-list/build_inteldb.py b/scripts/intel-affected-processor-list/build_inteldb.py new file mode 100644 index 0000000..a6dd690 --- /dev/null +++ b/scripts/intel-affected-processor-list/build_inteldb.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python3 +"""Build INTELDB from a local clone of Intel's affected processor list history.""" + +import argparse +import csv +import io +from pathlib import Path +import re +import subprocess +import sys + +from parse_inteldb_csv import format_cpuid, format_db, parse_csv + + +CSV_PATH = 'Intel_affected_processor_list.csv' + + +def parse_db(stream): + """Recover legacy entries, adapted from compare_inteldb_history.py.""" + entries = {} + in_db = False + for line in stream: + if '%%% INTELDB' in line: + in_db = True + continue + if not in_db: + continue + if '%%% ENDOFINTELDB' in line: + break + if not line.startswith('# 0x'): + continue + fields = line[2:].strip().rstrip(',').split(',') + cpuid = format_cpuid(fields.pop(0)) + qualifier = '' + if fields and re.fullmatch(r'H=[01]', fields[0]): + qualifier = fields.pop(0) + vulns = {} + for field in fields: + cves, status = field.split('=', 1) + for cve in cves.split('+'): + vulns[cve] = status + entries[(cpuid, qualifier)] = vulns + if not entries: + raise ValueError('No entries found in baseline INTELDB') + return entries + + +def merge_snapshot(merged, snapshot): + """Newest snapshot wins per CPUID; retain CPUs absent from that snapshot. + + Replace all qualifiers for a present CPUID together. Otherwise historical + unqualified entries survive when explicit H=0/H=1 entries are introduced, + and runtime lookup can incorrectly fall back to obsolete data. + """ + present = {cpuid for cpuid, _ in snapshot} + for key in list(merged): + if key[0] in present: + del merged[key] + merged.update(snapshot) + + +def git(repo, *args): + return subprocess.run( + ['git', '-C', repo, *args], check=True, stdout=subprocess.PIPE, + stderr=subprocess.PIPE, encoding='utf-8-sig', + ).stdout + + +def build_history(repo, ref='HEAD', baseline=None): + # Resolve once so a concurrent fetch/checkout cannot change the input. + revision = git(repo, 'rev-parse', '--verify', f'{ref}^{{commit}}').strip() + if git(repo, 'rev-parse', '--is-shallow-repository').strip() == 'true': + raise ValueError('Intel repository is shallow; use a full clone to retain historical CPUs') + # Consume Git's ordering directly, never a glob sorted by commit hash. + commits = git(repo, 'log', '--reverse', '--topo-order', '--format=%H', + revision, '--', CSV_PATH).splitlines() + # Always parse the selected tip last, including when it is a merge commit + # that was omitted by path-history simplification. + commits = [commit for commit in commits if commit != revision] + [revision] + merged = dict(baseline or {}) + for commit in commits: + try: + snapshot = parse_csv(io.StringIO(git(repo, 'show', f'{commit}:{CSV_PATH}'))) + except (ValueError, csv.Error) as error: + raise ValueError(f'{commit}: {error}') from error + merge_snapshot(merged, snapshot) + print(f'{commit[:12]}: {len(snapshot)} entries; {len(merged)} retained', file=sys.stderr) + return merged, revision + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument('repo', help='Full local clone of intel/Intel-affected-processor-list') + parser.add_argument('output_file', nargs='?', help='Defaults to stdout') + parser.add_argument('--ref', default='HEAD', help='Revision to build (default: HEAD)') + parser.add_argument('--base-db', help='Existing INTELDB retaining legacy CPUs absent from CSV history') + args = parser.parse_args() + try: + header = Path(__file__).resolve().with_name('header.txt').read_text(encoding='utf-8') + baseline = None + if args.base_db: + with open(args.base_db, encoding='utf-8') as stream: + baseline = parse_db(stream) + entries, revision = build_history(args.repo, args.ref, baseline) + output = format_db(entries, f'Merged Intel CSV history through {revision} (newest CPUID data wins)') + output = header.rstrip('\n') + '\n' + output + if args.output_file: + with open(args.output_file, 'w', encoding='utf-8') as stream: + stream.write(output) + else: + sys.stdout.write(output) + except subprocess.CalledProcessError as error: + parser.exit(1, f'ERROR: git: {error.stderr.strip()}\n') + except (OSError, ValueError, csv.Error) as error: + parser.exit(1, f'ERROR: {error}\n') + + +if __name__ == '__main__': + main() diff --git a/scripts/intel-affected-processor-list/header.txt b/scripts/intel-affected-processor-list/header.txt new file mode 100644 index 0000000..5808ea3 --- /dev/null +++ b/scripts/intel-affected-processor-list/header.txt @@ -0,0 +1,18 @@ +# vim: set ts=4 sw=4 sts=4 et: +# +# N: Not affected +# S: Affected, software fix +# H: Affected, hardware fix +# M: Affected, MCU update needed +# B: Affected, BIOS update needed +# X: Affected, no planned mitigation +# Y: Affected (no details available) +# MS: Affected, MCU + software fix +# HS: Affected, hardware + software fix +# HM: Affected, hardware + MCU fix +# +# Entries may have an optional hybrid qualifier after the CPUID: +# 0xCPUID,H=1,... matches only hybrid CPUs (CPUID.0x7.EDX[15]=1) +# 0xCPUID,H=0,... matches only non-hybrid CPUs (CPUID.0x7.EDX[15]=0) +# 0xCPUID,... matches any CPU (no qualifier = fallback) +# diff --git a/scripts/intel-affected-processor-list/historical_records.db b/scripts/intel-affected-processor-list/historical_records.db new file mode 100644 index 0000000..ba4cff8 --- /dev/null +++ b/scripts/intel-affected-processor-list/historical_records.db @@ -0,0 +1,150 @@ +# vim: set ts=4 sw=4 sts=4 et: +# Historical records to be merged with new ones from Git +# +# N: Not affected +# S: Affected, software fix +# H: Affected, hardware fix +# M: Affected, MCU update needed +# B: Affected, BIOS update needed +# X: Affected, no planned mitigation +# Y: Affected (no details available) +# MS: Affected, MCU + software fix +# HS: Affected, hardware + software fix +# HM: Affected, hardware + MCU fix +# +# Entries may have an optional hybrid qualifier after the CPUID: +# 0xCPUID,H=1,... matches only hybrid CPUs (CPUID.0x7.EDX[15]=1) +# 0xCPUID,H=0,... matches only non-hybrid CPUs (CPUID.0x7.EDX[15]=0) +# 0xCPUID,... matches any CPU (no qualifier = fallback) +# +# %%% INTELDB +# +# XSLX source: https://software.intel.com/content/dam/www/public/us/en/documents/affected-processors-transient-execution-attacks-by-cpu-aug02.xlsx +# +# 0x000206A7,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=N, +# 0x000206D6,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=N, +# 0x000206D7,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=N, +# 0x00030673,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x00030678,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x00030679,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000306A9,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=Y, +# 0x000306C3,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=Y, +# 0x000306D4,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=Y,2020-0543=Y, +# 0x000306E4,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=N, +# 0x000306E7,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=N, +# 0x00040651,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=Y, +# 0x00040661,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=N,2020-0543=Y, +# 0x00040671,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=Y,2020-0543=Y, +# 0x000406A0,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000406C3,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000406C4,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000406D8,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000406E3,2017-5715=MS,2017-5753=S,2017-5754=S,2018-12126=MS,2018-12127=MS,2018-12130=MS,2018-12207=S,2018-3615=MS,2018-3620=MS,2018-3639=MS,2018-3640=M,2018-3646=MS,2019-11135=MS,2020-0543=MS, +# 0x0005065A,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=S,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x00050662,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=Y,2018-12130=Y,2018-12207=Y,2018-3615=Y,2018-3620=Y,2018-3639=Y,2018-3640=Y,2018-3646=Y,2019-11135=Y,2020-0543=N, +# 0x000506A0,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000506C9,2017-5715=MS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=MS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000506D0,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x00060650,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000606A0,2017-5715=Y,2017-5753=Y,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=Y,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x000606A4,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000606A5,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000606E1,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x0007065A,2017-5715=Y,2017-5753=Y,2017-5754=Y,2018-12126=Y,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=N,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x00080660,2017-5715=Y,2017-5753=Y,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=Y,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N, +# 0x00080664,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000806A0,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=HM,2018-12127=N,2018-12130=N,2018-12207=S,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000806A1,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=HM,2018-12127=N,2018-12130=N,2018-12207=S,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000806C0,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000806D0,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x00090670,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x00090671,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x00090673,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x00090674,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000906A0,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=MS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000906A2,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=MS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=N, +# 0x000A0650,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=S,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=M,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000A0651,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=S,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=M,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000A0670,2017-5715=HS,2017-5753=S,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=N,2018-3615=N,2018-3620=N,2018-3639=HS,2018-3640=N,2018-3646=N,2019-11135=N,2020-0543=N,2022-40982=M, +# 0x000A0680,2017-5715=Y,2017-5753=Y,2017-5754=N,2018-12126=N,2018-12127=N,2018-12130=N,2018-12207=Y,2018-3615=N,2018-3620=N,2018-3639=Y,2018-3640=Y,2018-3646=N,2019-11135=N,2020-0543=N, +# +# HTML source: https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html +# (merged with an old version of the git repo) +# +# 0x000306F2,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=X,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=N,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x000306F4,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=X,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x000406F1,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=X,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x00050653,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=S,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=X,2020-0551_stale=X,2020-0549=M,2020-8696=MS,2020-0548=MS,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x00050654,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=M,2022-26373=N,2022-21233=N,2022-29901=S,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=X,2020-0551_stale=X,2020-0549=M,2020-8696=MS,2020-0548=MS,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x00050656,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=M,2022-26373=S,2022-21233=N,2022-38090=N,2022-29901=N,2022-28693=S,2022-21166=MS,2022-21125=N,2022-21123=N,2022-2118=N,2022-0001=S,2022-0002=S,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=M,2020-24512=N,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=X,2020-0551_stale=X,2020-0549=M,2020-8696=MS,2020-0548=MS,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x00050657,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=M,2022-26373=S,2022-21233=N,2022-38090=N,2022-29901=N,2022-28693=S,2022-21166=MS,2022-21125=N,2022-21123=N,2022-2118=N,2022-0001=S,2022-0002=S,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=M,2020-24512=N,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=X,2020-0551_stale=X,2020-0549=M,2020-8696=MS,2020-0548=MS,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x0005065B,2024-45332=M,2024-28956_IBPB=M,2024-28956_GH=S,2024-28956_cBPF=S,2024-31068=M,2024-36242=N,2024-23984=M,2024-25939=M,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=M,2022-26373=S,2022-21233=N,2022-29901=N,2022-28693=S,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=S,2022-0002=S,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=M,2020-24512=N,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=X,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x00050663,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=X,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x00050664,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=X,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x00050665,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=MS,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=X,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=X,2020-0551_zero=X,2020-0551_stale=X,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 0x000506CA,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=S,2022-29901=N,2022-28693=N,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=N,2022-0002=S,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=M,2020-8695=M,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=MS,2018-3640=N,2017-5754=N,2017-5715=MS,2017-5753=S, +# 0x000506E3,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=M,2022-26373=N,2022-21233=N,2022-29901=S,2022-28693=N,2022-21166=MS,2022-21125=MS,2022-21123=MS,2022-21180=MS,2022-0001=N,2022-0002=N,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=M,2020-24513=N,2020-8695=M,2020-8698=N,2020-0543=MS,2022-21127=MS,2020-0550=N,2020-0551_zero=S,2020-0551_stale=S,2020-0549=M,2020-8696=MS,2020-0548=MS,2018-12207=S,2019-11135=MS,2019-1125=S,2018-12127=MS,2018-12126=MS,2018-12130=MS,2018-3615=MS,2018-3620=MS,2018-3646=MS,2018-3639=MS,2018-3640=M,2017-5754=S,2017-5715=MS,2017-5753=S, +# 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0x000B06A2,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=M,2023-39368=N,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06A3,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=M,2023-39368=N,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06A8,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=M,2023-39368=N,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06D1,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06E0,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=N,2023-39368=M,2023-23583=N,2022-40982=N,2022-26373=N,2022-21233=N,2022-29901=N,2022-28693=N,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06F2,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=M,2023-39368=M,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000B06F5,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=MS,2023-22655=N,2023-38575=M,2023-39368=M,2023-23583=M,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C0652,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C0662,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=S,2022-21233=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C0664,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=N,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=S,2022-21233=S,2022-38090=S,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-2118=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C06C2,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=S,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=S,2022-21233=N,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C06C3,2024-45332=N,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=N,2024-36242=S,2024-23984=N,2024-25939=N,2023-28746=N,2023-22655=N,2023-38575=N,2023-39368=N,2023-23583=N,2022-40982=N,2022-26373=S,2022-21233=N,2022-29901=N,2022-28693=HS,2022-21166=N,2022-21125=N,2022-21123=N,2022-21180=N,2022-0001=HS,2022-0002=HS,2021-0145=N,2021-33120=N,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# 0x000C06F2,2024-45332=M,2024-28956_IBPB=N,2024-28956_GH=N,2024-28956_cBPF=N,2024-31068=M,2021-0089=S,2021-0086=S,2020-24511=N,2020-24512=N,2020-24513=N,2020-8695=N,2020-8698=N,2020-0543=N,2022-21127=N,2020-0550=N,2020-0551_zero=N,2020-0551_stale=N,2020-0549=N,2020-8696=N,2020-0548=N,2018-12207=N,2019-11135=N,2019-1125=S,2018-12127=N,2018-12126=N,2018-12130=N,2018-3615=N,2018-3620=N,2018-3646=N,2018-3639=HS,2018-3640=N,2017-5754=N,2017-5715=HS,2017-5753=S, +# +# %%% ENDOFINTELDB diff --git a/scripts/intel-affected-processor-list/parse_inteldb_csv.py b/scripts/intel-affected-processor-list/parse_inteldb_csv.py new file mode 100644 index 0000000..8961e48 --- /dev/null +++ b/scripts/intel-affected-processor-list/parse_inteldb_csv.py @@ -0,0 +1,286 @@ +#!/usr/bin/env python3 +""" +Parse Intel's affected processor list CSV into the checker's INTELDB format. + +Recovered from smc-new2/c/scripts/inteldb/parse_inteldb_csv.py. Uses explicit +hybrid identification when available, with codename inference for old CSVs. +""" + +import argparse +import csv +import re +import sys +from collections import OrderedDict + + +# Only used for historical CSVs without the hybrid identification column. +HYBRID_CODENAMES = {'alder lake', 'raptor lake'} +NON_HYBRID_CODENAMES = {'catlow', 'arizona beach', 'alder lake n', 'twin lake'} + +STATUS_MAP = { + 'not affected': 'N', + 'affected': 'Y', + 'mcu': 'M', + 'software': 'S', + 'hardware': 'H', + 'bios': 'B', + 'no planned mitigation': 'X', + 'mcu+software': 'MS', + 'mcu + software': 'MS', + 'hardware+software': 'HS', + 'hardware + software': 'HS', + 'hardware+mcu': 'HM', + 'hardware + mcu': 'HM', +} + +STATUS_SEVERITY = { + 'N': 0, 'S': 1, 'M': 2, 'B': 2, 'H': 3, + 'MS': 3, 'MB': 3, 'HS': 4, 'HM': 4, 'MBS': 4, 'HMS': 5, 'X': 6, 'Y': 6, +} + + +def normalize_status(status_text): + """Convert status text to db code.""" + s = status_text.strip().lower() + s = s.replace('\xa0', ' ').strip() + s = re.sub(r'(\d+)$', '', s).strip() + s = re.sub(r'[_\s]+', ' ', s).strip() + if not s: + return None + if s in STATUS_MAP: + return STATUS_MAP[s] + if 'not affected' in s: + return 'N' + if 'no planned' in s: + return 'X' + s = re.sub(r'\s*\+\s*', '+', s) + parts = set() + for part in s.split('+'): + part = part.strip() + if part in ('mcu', 'microcode'): + parts.add('M') + elif part in ('software', 'sw', 'soft'): + parts.add('S') + elif part in ('hardware', 'hw'): + parts.add('H') + elif part == 'bios': + parts.add('B') + elif part == 'mcu bios': + parts.update(('M', 'B')) + else: + print(f"WARNING: unknown status part '{part}' in '{status_text}' -> treating as Y", file=sys.stderr) + return 'Y' + return ''.join(code for code in ('H', 'M', 'B', 'S') if code in parts) or 'Y' + + +def worst_case_status(s1, s2): + sev1 = STATUS_SEVERITY.get(s1, 6) + sev2 = STATUS_SEVERITY.get(s2, 6) + return s1 if sev1 >= sev2 else s2 + + +def expand_combined_cves(vulns): + """Expand combined CVE keys into individual entries.""" + expanded = OrderedDict() + for key, status in vulns.items(): + for cve in key.split('+'): + expanded[cve] = status + return expanded + + +def parse_cpuid_values(cpuid_cell): + """Parse explicit CPUID lists, excluding parenthesized platform IDs.""" + text = re.sub(r'\([^)]*\)', '', cpuid_cell).strip() + if not text: + return [] + cpuids = [] + for part in re.split(r'[,\s]+', text): + if part in ('', '-'): + continue + if not re.fullmatch(r'(?:0[xX])?[0-9a-fA-F]{5,8}', part): + raise ValueError(f'Unsupported CPUID value {part!r} in {cpuid_cell!r}') + cpuid = format_cpuid(part) + if cpuid not in cpuids: + cpuids.append(cpuid) + return cpuids + + +def extract_cve_keys(header_row, first_cve_col=0): + """Extract CVE keys by header text, including combined/duplicate columns.""" + cve_keys = [] + cve_count = {} + for i in range(first_cve_col, len(header_row)): + cve_matches = re.findall(r'CVE[- ](\d{4}[- ]\d+)', header_row[i]) + if not cve_matches: + continue + cve_ids = list(dict.fromkeys(m.replace(' ', '-') for m in cve_matches)) + key = '+'.join(cve_ids) + cve_count[key] = cve_count.get(key, 0) + 1 + cve_keys.append((i, key)) + + final_keys = [] + seen_count = {} + for idx, key in cve_keys: + if cve_count[key] > 1: + seen_count[key] = seen_count.get(key, 0) + 1 + header_text = header_row[idx].lower() + if 'ibpb' in header_text: + suffix = 'IBPB' + elif 'guest' in header_text or 'host' in header_text: + suffix = 'GH' + elif 'cbpf' in header_text: + suffix = 'cBPF' + elif 'zero' in header_text: + suffix = 'zero' + elif 'stale' in header_text: + suffix = 'stale' + elif 'rrsba' in header_text: + suffix = 'RRSBA' + elif 'rsbu' in header_text or 'rsba' in header_text: + suffix = 'RSBU' + else: + suffix = f'v{seen_count[key]}' + final_keys.append((idx, f'{key}_{suffix}')) + else: + final_keys.append((idx, key)) + return final_keys + + +def infer_hybrid(codename): + """Infer hybrid status for old CSVs. Returns '0', '1', or None.""" + cn = codename.lower() + for name in NON_HYBRID_CODENAMES: + if name in cn: + return '0' + for name in HYBRID_CODENAMES: + if name in cn: + return '1' + return None + + +def parse_hybrid(text): + """Read Intel's explicit hybrid bit, accepting the optional core-type field. + + INTELDB describes processors at CPUID + hybrid-bit granularity. Core-type + rows sharing that key are worst-case merged, like segment-specific rows. + The core-type value is hexadecimal (20 = Atom, 40 = Core). + """ + text = text.strip() + if text.upper() in ('', 'NA', 'N/A'): + return None + match = re.fullmatch( + r'CPUID\.0x7\.EDX\[15\]\s*=\s*([01])' + r'(?:\s*-\s*CPUID\.0x1A\.EAX\[31:24\]\s*=\s*(?:0x)?(?:20|40))?', + text, re.IGNORECASE, + ) + if not match: + raise ValueError(f'Unsupported CPUID Hybrid Identification: {text!r}') + return match.group(1) + + +def merge_worst_case(vulns1, vulns2): + merged = OrderedDict(vulns1) + for cve, status in vulns2.items(): + merged[cve] = worst_case_status(merged[cve], status) if cve in merged else status + return merged + + +def format_cpuid(cpuid_hex): + return f'0x{int(cpuid_hex, 16):08X}' + + +def parse_csv(stream): + """Return {(normalized CPUID, hybrid qualifier): vulnerability mapping}.""" + reader = csv.reader(stream) + header = next(reader, []) + header_lower = [h.lstrip('\ufeff').strip().lower() for h in header] + if 'cpuid' not in header_lower: + raise ValueError('Cannot find CPUID column') + cpuid_col = header_lower.index('cpuid') + codename_col = next((i for i, h in enumerate(header_lower) + if 'code name' in h or 'microarchitecture' in h), None) + hybrid_col = (header_lower.index('cpuid hybrid identification') + if 'cpuid hybrid identification' in header_lower else None) + cve_keys = extract_cve_keys(header) + if not cve_keys: + raise ValueError('Cannot find vulnerability columns') + + raw_entries = {} + for row in reader: + if not row or not any(cell.strip() for cell in row): + continue + if len(row) != len(header): + raise ValueError(f'CSV line {reader.line_num}: expected {len(header)} columns, got {len(row)}') + cpuids = parse_cpuid_values(row[cpuid_col]) + if not cpuids: + continue + if hybrid_col is not None: + hybrid = parse_hybrid(row[hybrid_col]) + else: + hybrid = infer_hybrid(row[codename_col]) if codename_col is not None else None + vuln_data = OrderedDict() + for col_idx, cve_key in cve_keys: + status = normalize_status(row[col_idx]) + if status: + vuln_data[cve_key] = status + vuln_data = expand_combined_cves(vuln_data) + for cpuid in cpuids: + key = (cpuid, hybrid) + raw_entries[key] = merge_worst_case(raw_entries.get(key, {}), vuln_data) + + cpuid_groups = {} + for (cpuid, hybrid), vulns in raw_entries.items(): + cpuid_groups.setdefault(cpuid, {})[hybrid] = vulns + + final_entries = {} + for cpuid, hybrid_map in cpuid_groups.items(): + # Historical inference only distinguished conflicting profiles. Keep + # that behavior for old CSVs, but never discard explicit qualifiers. + vuln_sets = {tuple(sorted(v.items())) for v in hybrid_map.values()} + if hybrid_col is None and len(vuln_sets) == 1: + final_entries[(cpuid, '')] = next(iter(hybrid_map.values())) + else: + for hybrid, vulns in hybrid_map.items(): + qualifier = f'H={hybrid}' if hybrid is not None else '' + final_entries[(cpuid, qualifier)] = vulns + if not final_entries: + raise ValueError('No processor entries found') + return final_entries + + +def format_db(entries, description='Parsed from Intel affected processor list CSV (GitHub)'): + lines = [ + f'# {description}', + '# Source: https://github.com/intel/Intel-affected-processor-list', + '#', + '# %%% INTELDB', + ] + for (cpuid, qualifier), vulns in sorted(entries.items()): + fields = [cpuid] + ([qualifier] if qualifier else []) + fields.extend(f'{cve}={status}' for cve, status in vulns.items()) + lines.append('# ' + ','.join(fields) + ',') + lines.append('# %%% ENDOFINTELDB') + return '\n'.join(lines) + '\n' + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument('csv_file') + parser.add_argument('output_file', nargs='?') + args = parser.parse_args() + try: + with open(args.csv_file, encoding='utf-8-sig', newline='') as stream: + entries = parse_csv(stream) + output = format_db(entries) + if args.output_file: + with open(args.output_file, 'w', encoding='utf-8') as stream: + stream.write(output) + else: + sys.stdout.write(output) + print(f'Parsed {len(entries)} processor entries', file=sys.stderr) + except (OSError, ValueError, csv.Error) as error: + parser.exit(1, f'ERROR: {error}\n') + + +if __name__ == '__main__': + main() diff --git a/scripts/intel-affected-processor-list/test_inteldb.py b/scripts/intel-affected-processor-list/test_inteldb.py new file mode 100644 index 0000000..2d859cc --- /dev/null +++ b/scripts/intel-affected-processor-list/test_inteldb.py @@ -0,0 +1,152 @@ +"""Regression cases for processor identity and historical database updates.""" + +import csv +import io +import unittest +from unittest.mock import patch + +from build_inteldb import build_history, merge_snapshot, parse_db +from parse_inteldb_csv import format_db, parse_csv, parse_cpuid_values + + +HYBRID = 'CPUID Hybrid Identification' +RFDS = 'Register File Data Sampling - CVE-2023-28746' +REPTAR = 'Reptar - CVE-2023-23583' + + +def csv_text(headers, rows): + stream = io.StringIO(newline='') + writer = csv.writer(stream) + writer.writerow(headers) + writer.writerows(rows) + return stream.getvalue() + + +def parse(headers, rows): + return parse_csv(io.StringIO(csv_text(headers, rows))) + + +class ParserTests(unittest.TestCase): + def test_explicit_identity_overrides_codename(self): + # Deliberately misleading names prove the explicit field wins. + entries = parse(['Code Name(s)', HYBRID, RFDS, 'CPUID'], [ + ['Catlow', 'CPUID.0x7.EDX[15]=1', 'MCU+Software', '90675'], + ['Alder Lake S', 'CPUID.0x7.EDX[15]=0 - CPUID.0x1A.EAX[31:24]=40', + 'Not Affected', '90675'], + ]) + self.assertEqual(entries[('0x00090675', 'H=1')]['2023-28746'], 'MS') + self.assertEqual(entries[('0x00090675', 'H=0')]['2023-28746'], 'N') + self.assertNotIn(('0x00090675', ''), entries) + + def test_arizona_beach_and_alder_lake_u(self): + entries = parse(['CPUID', HYBRID, REPTAR], [ + ['906A4', 'CPUID.0x7.EDX[15]=0', 'Not Affected'], + ['906A4', 'CPUID.0x7.EDX[15]=1', 'MCU'], + ]) + self.assertEqual(entries[('0x000906A4', 'H=0')]['2023-23583'], 'N') + self.assertEqual(entries[('0x000906A4', 'H=1')]['2023-23583'], 'M') + + def test_single_and_identical_explicit_profiles_keep_qualifiers(self): + entries = parse(['CPUID', HYBRID, RFDS], [ + ['90672', 'CPUID.0x7.EDX[15]=1', 'MCU+Software'], + ['90675', 'CPUID.0x7.EDX[15]=1', 'Not Affected'], + ['90675', 'CPUID.0x7.EDX[15]=0', 'Not Affected'], + ]) + self.assertEqual(set(entries), { + ('0x00090672', 'H=1'), ('0x00090675', 'H=0'), ('0x00090675', 'H=1'), + }) + + def test_na_does_not_infer_hybrid(self): + for value in ('NA', 'N/A', ''): + with self.subTest(value=value): + entries = parse(['CPUID', 'Code Name(s)', HYBRID, RFDS], [ + ['90675', 'Alder Lake S', value, 'Not Affected'], + ]) + self.assertEqual(set(entries), {('0x00090675', '')}) + + def test_legacy_inference(self): + entries = parse(['CPUID', 'Code Name(s)', RFDS], [ + ['90675', 'Alder Lake S', 'MCU+Software'], + ['90675', 'Catlow', 'Not Affected'], + ['306F2', 'Haswell', 'Not Affected'], + ]) + self.assertEqual(set(entries), { + ('0x00090675', 'H=0'), ('0x00090675', 'H=1'), ('0x000306F2', ''), + }) + + def test_unknown_identity_and_truncated_rows_fail(self): + with self.assertRaisesRegex(ValueError, 'Hybrid Identification'): + parse(['CPUID', HYBRID, RFDS], [['90675', 'unknown', 'Not Affected']]) + with self.assertRaisesRegex(ValueError, 'expected 3 columns'): + parse(['CPUID', HYBRID, RFDS], [['90675', 'NA']]) + + def test_platform_masks_are_not_cpuids(self): + self.assertEqual(parse_cpuid_values('806F5 - 806F8 (PID 0x87)'), + ['0x000806F5', '0x000806F8']) + self.assertEqual(parse_cpuid_values('A06D1 (PID 0x00000095)'), ['0x000A06D1']) + + def test_combined_cves_and_duplicate_columns(self): + entries = parse([ + 'CPUID', 'L1TF - CVE-2018-3615 - CVE-2018-3620 - CVE-2018-3646', + 'ITS (IBPB) - CVE-2024-28956', 'ITS (Guest-Host) - CVE-2024-28956', + 'ITS cBPF - CVE-2024-28956', + ], [['90675', 'Not Affected', 'MCU', 'Software', 'Not Affected']]) + self.assertEqual(entries[('0x00090675', '')], { + '2018-3615': 'N', '2018-3620': 'N', '2018-3646': 'N', + '2024-28956_IBPB': 'M', '2024-28956_GH': 'S', '2024-28956_cBPF': 'N', + }) + + def test_segment_and_core_type_rows_merge_conservatively(self): + entries = parse(['CPUID', HYBRID, 'Segment', RFDS], [ + ['B06E0', 'CPUID.0x7.EDX[15]=0 - CPUID.0x1A.EAX[31:24]=20', + 'Embedded', 'MCU_BIOS+Software'], + ['B06E0', 'CPUID.0x7.EDX[15]=0 - CPUID.0x1A.EAX[31:24]=40', + 'Mobile', 'Not Affected'], + ]) + self.assertEqual(entries[('0x000B06E0', 'H=0')]['2023-28746'], 'MBS') + self.assertEqual(parse_db(io.StringIO(format_db(entries))), entries) + + +class HistoryTests(unittest.TestCase): + def test_new_snapshot_replaces_profiles_and_preserves_absent_cpus(self): + merged = { + ('0x00090675', ''): {'2023-28746': 'N'}, + ('0x000306F2', ''): {'2023-28746': 'N'}, + } + snapshot = { + ('0x00090675', 'H=1'): {'2023-28746': 'MS'}, + ('0x00090675', 'H=0'): {'2023-28746': 'N'}, + } + merge_snapshot(merged, snapshot) + self.assertNotIn(('0x00090675', ''), merged) + self.assertIn(('0x000306F2', ''), merged) + merge_snapshot(merged, {('0x00090675', ''): {'2023-28746': 'M'}}) + self.assertNotIn(('0x00090675', 'H=0'), merged) + self.assertNotIn(('0x00090675', 'H=1'), merged) + + def test_build_uses_git_order_not_hash_order_and_tip_last(self): + old = csv_text(['CPUID', RFDS], [['90675', 'Not Affected'], ['306F2', 'Not Affected']]) + new = csv_text(['CPUID', HYBRID, RFDS], [['90675', 'CPUID.0x7.EDX[15]=1', 'MCU']]) + tip = csv_text(['CPUID', HYBRID, RFDS], [['90675', 'CPUID.0x7.EDX[15]=1', 'MCU+Software']]) + with patch('build_inteldb.git', side_effect=[ + 'tip\n', 'false\n', 'ffff\naaaa\n', old, new, tip, + ]) as run_git: + entries, revision = build_history('repo') + self.assertEqual(revision, 'tip') + self.assertEqual(entries[('0x00090675', 'H=1')]['2023-28746'], 'MS') + self.assertNotIn(('0x00090675', ''), entries) + self.assertIn(('0x000306F2', ''), entries) + self.assertEqual([call.args[2] for call in run_git.call_args_list[3:]], [ + 'ffff:Intel_affected_processor_list.csv', + 'aaaa:Intel_affected_processor_list.csv', + 'tip:Intel_affected_processor_list.csv', + ]) + + def test_shallow_clone_rejected(self): + with patch('build_inteldb.git', side_effect=['tip\n', 'true\n']): + with self.assertRaisesRegex(ValueError, 'shallow'): + build_history('repo') + + +if __name__ == '__main__': + unittest.main()