mirror of
https://github.com/speed47/spectre-meltdown-checker.git
synced 2025-07-15 23:31:22 +02:00
Added support for TAA related vulnerabilities
This commit is contained in:
Agata Gruza
committed by
Stéphane Lesimple
Stéphane Lesimple
parent
f5ec320fe5
commit
d623524342
@ -78,7 +78,7 @@ show_usage()
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--batch prometheus produce output for consumption by prometheus-node-exporter
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--variant VARIANT specify which variant you'd like to check, by default all variants are checked
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VARIANT can be one of 1, 2, 3, 3a, 4, l1tf, msbds, mfbds, mlpds, mdsum
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VARIANT can be one of 1, 2, 3, 3a, 4, l1tf, msbds, mfbds, mlpds, mdsum, taa
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can be specified multiple times (e.g. --variant 2 --variant 3)
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--cve [cve1,cve2,...] specify which CVE you'd like to check, by default all supported CVEs are checked
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--hw-only only check for CPU information, don't check for any variant
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@ -157,7 +157,7 @@ global_critical=0
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global_unknown=0
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nrpe_vuln=''
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supported_cve_list='CVE-2017-5753 CVE-2017-5715 CVE-2017-5754 CVE-2018-3640 CVE-2018-3639 CVE-2018-3615 CVE-2018-3620 CVE-2018-3646 CVE-2018-12126 CVE-2018-12130 CVE-2018-12127 CVE-2019-11091'
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supported_cve_list='CVE-2017-5753 CVE-2017-5715 CVE-2017-5754 CVE-2018-3640 CVE-2018-3639 CVE-2018-3615 CVE-2018-3620 CVE-2018-3646 CVE-2018-12126 CVE-2018-12130 CVE-2018-12127 CVE-2019-11091 CVE-2019-11135'
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# find a sane command to print colored messages, we prefer `printf` over `echo`
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# because `printf` behavior is more standard across Linux/BSD
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@ -279,6 +279,7 @@ cve2name()
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CVE-2018-12130) echo "ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)";;
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CVE-2018-12127) echo "RIDL, microarchitectural load port data sampling (MLPDS)";;
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CVE-2019-11091) echo "RIDL, microarchitectural data sampling uncacheable memory (MDSUM)";;
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CVE-2019-11135) echo "Transactional Synchronization Extensions (TSX) Asynchronous Abort (TAA)";;
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*) echo "$0: error: invalid CVE '$1' passed to cve2name()" >&2; exit 255;;
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esac
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}
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@ -300,6 +301,7 @@ _is_cpu_vulnerable_cached()
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CVE-2018-12130) return $variant_mfbds;;
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CVE-2018-12127) return $variant_mlpds;;
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CVE-2019-11091) return $variant_mdsum;;
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CVE-2019-11135) return $variant_taa;;
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*) echo "$0: error: invalid variant '$1' passed to is_cpu_vulnerable()" >&2; exit 255;;
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esac
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}
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@ -326,6 +328,7 @@ is_cpu_vulnerable()
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variant_mfbds=''
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variant_mlpds=''
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variant_mdsum=''
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variant_taa=''
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if is_cpu_mds_free; then
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[ -z "$variant_msbds" ] && variant_msbds=immune
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@ -335,6 +338,11 @@ is_cpu_vulnerable()
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_debug "is_cpu_vulnerable: cpu not affected by Microarchitectural Data Sampling"
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fi
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if is_cpu_taa_free; then
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[ -z "$variant_taa" ] && variant_taa=immune
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_debug "is_cpu_vulnerable: cpu not affected by TSX Asynhronous Abort"
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fi
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if is_cpu_specex_free; then
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variant1=immune
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variant2=immune
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@ -346,6 +354,7 @@ is_cpu_vulnerable()
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variant_mfbds=immune
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variant_mlpds=immune
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variant_mdsum=immune
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variant_taa=immune
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elif is_intel; then
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# Intel
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# https://github.com/crozone/SpectrePoC/issues/1 ^F E5200 => spectre 2 not vulnerable
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@ -528,6 +537,7 @@ is_cpu_vulnerable()
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[ "$variant_mfbds" = "immune" ] && variant_mfbds=1 || variant_mfbds=0
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[ "$variant_mlpds" = "immune" ] && variant_mlpds=1 || variant_mlpds=0
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[ "$variant_mdsum" = "immune" ] && variant_mdsum=1 || variant_mdsum=0
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[ "$variant_taa" = "immune" ] && variant_taa=1 || variant_taa=0
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variantl1tf_sgx="$variantl1tf"
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# even if we are vulnerable to L1TF, if there's no SGX, we're safe for the original foreshadow
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[ "$cpuid_sgx" = 0 ] && variantl1tf_sgx=1
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@ -616,6 +626,27 @@ is_cpu_mds_free()
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return 1
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}
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is_cpu_taa_free()
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{
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# return true (0) if the CPU isn't affected by tsx asynchronnous aborts, false (1) if it does.
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# There are three types of processors that do not require additional mitigations.
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# 1. CPUs that do not support Intel TSX are not affected.
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# 2. CPUs that enumerate IA32_ARCH_CAPABILITIES[TAA_NO] (bit 8)=1 are not affected.
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# 3. CPUs that support Intel TSX and do not enumerate IA32_ARCH_CAPABILITIES[MDS_NO] (bit 5)=1
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# do not need additional mitigations beyond what is already required to mitigate MDS.
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if ! is_intel; then
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return 0
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# is intel
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elif [ "$capabilities_taa_no" = 0 ] || \
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[ "$rtm" = 0]; then
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return 0
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fi
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return 1
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}
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is_cpu_ssb_free()
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{
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# return true (0) if the CPU isn't affected by speculative store bypass, false (1) if it does.
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@ -885,8 +916,9 @@ while [ -n "$1" ]; do
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mlpds) opt_cve_list="$opt_cve_list CVE-2018-12127"; opt_cve_all=0;;
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mdsum) opt_cve_list="$opt_cve_list CVE-2019-11091"; opt_cve_all=0;;
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l1tf) opt_cve_list="$opt_cve_list CVE-2018-3615 CVE-2018-3620 CVE-2018-3646"; opt_cve_all=0;;
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taa) opt_cve_list="$opt_cve_list CVE-2019-11135"; opt_cve_all=0;;
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*)
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echo "$0: error: invalid parameter '$2' for --variant, expected either 1, 2, 3, 3a, 4, msbds, mfbds, mlpds, mdsum, or l1tf" >&2;
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echo "$0: error: invalid parameter '$2' for --variant, expected either 1, 2, 3, 3a, 4, msbds, mfbds, mlpds, mdsum, taa or l1tf" >&2;
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exit 255
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;;
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esac
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@ -2477,6 +2509,22 @@ check_cpu()
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fi
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fi
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if is_intel; then
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_info " * TSX Asynchronous Abort"
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_info_nol " * TSX support is available: "
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read_cpuid 0x7 $EDX 11 1 1; ret=$?
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if [ $ret -eq 0 ]; then
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rtm=1
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pstatus green YES "TSX RTM feature bit"
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elif [ $ret -eq 2 ]; then
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rtm=-1
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pstatus yellow UNKNOWN "is cpuid kernel module available?"
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else
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rtm=0
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pstatus yellow NO
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fi
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fi
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if is_intel; then
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_info " * Enhanced IBRS (IBRS_ALL)"
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_info_nol " * CPU indicates ARCH_CAPABILITIES MSR availability: "
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@ -2494,6 +2542,7 @@ check_cpu()
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fi
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_info_nol " * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: "
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capabilities_taa_no=-1
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capabilities_mds_no=-1
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capabilities_rdcl_no=-1
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capabilities_ibrs_all=-1
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@ -2504,6 +2553,7 @@ check_cpu()
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pstatus yellow UNKNOWN
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elif [ "$cpuid_arch_capabilities" != 1 ]; then
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capabilities_rdcl_no=0
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capabilities_taa_no=0
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capabilities_mds_no=0
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capabilities_ibrs_all=0
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capabilities_rsba=0
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@ -2536,6 +2586,7 @@ check_cpu()
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done
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capabilities=$val_cap_msr
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capabilities_rdcl_no=0
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capabilities_taa_no=0
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capabilities_mds_no=0
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capabilities_ibrs_all=0
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capabilities_rsba=0
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@ -2549,7 +2600,8 @@ check_cpu()
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[ $(( capabilities >> 3 & 1 )) -eq 1 ] && capabilities_l1dflush_no=1
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[ $(( capabilities >> 4 & 1 )) -eq 1 ] && capabilities_ssb_no=1
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[ $(( capabilities >> 5 & 1 )) -eq 1 ] && capabilities_mds_no=1
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_debug "capabilities says rdcl_no=$capabilities_rdcl_no ibrs_all=$capabilities_ibrs_all rsba=$capabilities_rsba l1dflush_no=$capabilities_l1dflush_no ssb_no=$capabilities_ssb_no mds_no=$capabilities_mds_no"
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[ $(( capabilities >> 8 & 1 )) -eq 1 ] && capabilities_taa_no=1
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_debug "capabilities says rdcl_no=$capabilities_rdcl_no ibrs_all=$capabilities_ibrs_all rsba=$capabilities_rsba l1dflush_no=$capabilities_l1dflush_no ssb_no=$capabilities_ssb_no mds_no=$capabilities_mds_no taa_no=$capabilities_taa_no"
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if [ "$capabilities_ibrs_all" = 1 ]; then
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if [ $cpu_mismatch -eq 0 ]; then
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pstatus green YES
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@ -2612,6 +2664,15 @@ check_cpu()
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else
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pstatus yellow NO
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fi
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_info_nol " * CPU explicitly indicates not being vulnerable to TSX Asynchrnonous Abort (TAA_NO): "
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if [ "$capabilities_taa_no" = -1 ]; then
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pstatus yellow UNKNOWN
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elif [ "$capabilities_taa_no" = 1 ]; then
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pstatus green YES
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else
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pstatus yellow NO
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fi
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fi
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_info_nol " * CPU supports Software Guard Extensions (SGX): "
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@ -4650,6 +4711,77 @@ check_mds_linux()
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fi
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}
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###################
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# TAA SECTION
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# Transactional Synchronization Extension (TSX) Asynchronous Abort
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check_CVE_2019_11135()
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{
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cve='CVE-2019-11135'
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check_taa $cve
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}
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# TSX Asynchronous Abort
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check_taa()
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{
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sys_interface_available=0
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cve=$1
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_info "\033[1;34m$cve aka '$(cve2name "$cve")'\033[0m"
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if [ "$opt_live" != 1 ]; then
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pstatus blue N/A "not testable in offline mode"
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pvulnstatus $cve UNK
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return
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fi
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if ! is_cpu_vulnerable "$cve" ; then
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# override status & msg in case CPU is not vulnerable after all
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pvulnstatus $cve OK "your CPU vendor reported your CPU model as not vulnerable"
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return
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fi
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if sys_interface_check '/sys/devices/system/cpu/vulnerabilities/tsx_async_abort'; then
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# this kernel has the /sys interface, trust it over everything
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sys_interface_available=1
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fi
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if [ "$sys_interface_available" = 1 ]; then
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if grep -Eq 'Not affected' "/sys/devices/system/cpu/vulnerabilities/tsx_async_abort"; then
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taa_mitigated=1
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elif grep -Eq 'Mitigation:' "/sys/devices/system/cpu/vulnerabilities/tsx_async_abort"; then
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if grep -Eq '(SMT mitigated|disabled)' "/sys/devices/system/cpu/vulnerabilities/tsx_async_abort"; then
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taa_mitigated=1
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else
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#Simultaneous multi-threading (aka SMT or HyperThreading) is enabled. System may be vulnerable in some environments.
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taa_mitigated=1
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_info_nol "* Disable SMT to have complete mitigation\n"
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fi
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elif grep -Eq 'Vulnerable' "/sys/devices/system/cpu/vulnerabilities/tsx_async_abort"; then
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taa_mitigated=0
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_info_nol "* For more info check Linux kernel Documentation/admin-guide/hw-vuln/tsx_async_abort.rst\n"
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else
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taa_mitigated=-1
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fi
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if grep -Eq 'no microcode' "/sys/devices/system/cpu/vulnerabilities/tsx_async_abort"; then
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taa_mitigated=0
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_info_nol "* CPU microcode is needed to mitigate the vulnerability\n"
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fi
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else
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pstatus yellow UNKNOWN "can't find or interpret /sys/devices/system/cpu/vulnerabilities/tsx_async_abort"
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taa_mitigated=-1
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fi
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if [ $taa_mitigated = 0 ];then
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pvulnstatus $cve VULN
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elif [ $taa_mitigated = 1 ]; then
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pvulnstatus $cve OK
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else
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pvulnstatus $cve UNK "further action may be needed to mitigate this vulnerability. For more info check Linux kernel Documentation/admin-guide/hw-vuln/tsx_async_abort.rst"
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fi
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}
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if [ "$opt_no_hw" = 0 ] && [ -z "$opt_arch_prefix" ]; then
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check_cpu
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check_cpu_vulnerabilities
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