mirror of
https://github.com/speed47/spectre-meltdown-checker.git
synced 2026-04-09 10:13:18 +02:00
chore: fix build workflow
built from commit de853fc801
dated 2026-04-08 23:00:40 +0200
by Stéphane Lesimple (speed47_github@speed47.net)
This commit is contained in:
github-actions[bot]
@@ -14,7 +14,7 @@
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"required": [
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"script_version", "format_version", "timestamp", "os", "mode",
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"run_as_root", "reduced_accuracy", "paranoid", "sysfs_only",
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"no_hw", "extra", "mocked"
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"extra", "mocked"
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],
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"additionalProperties": false,
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"properties": {
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@@ -56,10 +56,6 @@
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"description": "True when --sysfs-only was set: the script trusted the kernel's own sysfs report without independent detection.",
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"type": "boolean"
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},
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"no_hw": {
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"description": "True when --no-hw was set: hardware checks (MSR, CPUID) were skipped.",
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"type": "boolean"
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},
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"extra": {
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"description": "True when --extra was set: additional experimental checks were enabled.",
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"type": "boolean"
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@@ -131,118 +127,158 @@
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},
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"cpu": {
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"description": "CPU hardware identification and capability flags. Null when --no-hw is active.",
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"type": ["object", "null"],
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"required": [
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"vendor", "friendly_name", "family", "model", "stepping",
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"cpuid", "platform_id", "hybrid", "codename",
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"arm_part_list", "arm_arch_list", "capabilities"
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],
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"additionalProperties": false,
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"properties": {
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"vendor": {
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"description": "CPU vendor string, e.g. 'Intel', 'AuthenticAMD'.",
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"type": ["string", "null"]
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},
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"friendly_name": {
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"description": "Human-readable CPU model from /proc/cpuinfo, e.g. 'Intel(R) Core(TM) i7-9700K CPU @ 3.60GHz'.",
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"type": ["string", "null"]
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},
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"family": {
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"description": "CPU family number.",
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"type": ["integer", "null"]
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},
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"model": {
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"description": "CPU model number.",
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"type": ["integer", "null"]
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},
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"stepping": {
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"description": "CPU stepping number.",
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"type": ["integer", "null"]
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},
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"cpuid": {
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"description": "Full CPUID leaf 1 EAX value as a hex string, e.g. '0x000906ed'. Null on some ARM CPUs.",
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"type": ["string", "null"],
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"pattern": "^0x[0-9a-f]+$"
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},
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"platform_id": {
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"description": "Intel platform ID from MSR 0x17. Null on AMD and ARM.",
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"type": ["integer", "null"]
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},
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"hybrid": {
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"description": "Whether this is a hybrid CPU (P-cores + E-cores, e.g. Alder Lake). Null if undeterminable.",
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"type": ["boolean", "null"]
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},
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"codename": {
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"description": "Intel CPU codename, e.g. 'Coffee Lake'. Null on AMD and ARM.",
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"type": ["string", "null"]
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},
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"arm_part_list": {
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"description": "Space-separated list of ARM part numbers detected across cores. Null on x86.",
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"type": ["string", "null"]
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},
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"arm_arch_list": {
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"description": "Space-separated list of ARM architecture levels detected across cores. Null on x86.",
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"type": ["string", "null"]
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},
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"capabilities": {
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"description": "CPU feature flags detected via CPUID and MSR reads. Each value is true (present), false (absent), or null (not applicable or could not be read).",
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"description": "CPU hardware identification. Null when --no-hw is active. Contains an 'arch' discriminator ('x86' or 'arm') and a matching arch-specific sub-object with identification fields and capabilities.",
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"oneOf": [
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{ "type": "null" },
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{
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"type": "object",
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"description": "x86 CPU (Intel, AMD, Hygon).",
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"required": ["arch", "vendor", "friendly_name", "x86"],
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"additionalProperties": false,
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"properties": {
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"spec_ctrl": { "type": ["boolean", "null"], "description": "SPEC_CTRL MSR present (Intel; enables IBRS + IBPB via WRMSR)" },
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"ibrs": { "type": ["boolean", "null"], "description": "Indirect Branch Restricted Speculation" },
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"ibpb": { "type": ["boolean", "null"], "description": "Indirect Branch Prediction Barrier" },
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"ibpb_ret": { "type": ["boolean", "null"], "description": "IBPB on return (enhanced form)" },
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"stibp": { "type": ["boolean", "null"], "description": "Single Thread Indirect Branch Predictors" },
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"ssbd": { "type": ["boolean", "null"], "description": "Speculative Store Bypass Disable" },
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"l1d_flush": { "type": ["boolean", "null"], "description": "L1D cache flush instruction" },
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"md_clear": { "type": ["boolean", "null"], "description": "VERW clears CPU buffers (MDS mitigation)" },
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"arch_capabilities": { "type": ["boolean", "null"], "description": "IA32_ARCH_CAPABILITIES MSR is present" },
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"rdcl_no": { "type": ["boolean", "null"], "description": "Not susceptible to RDCL (Meltdown-like attacks)" },
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"ibrs_all": { "type": ["boolean", "null"], "description": "Enhanced IBRS always-on mode supported" },
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"rsba": { "type": ["boolean", "null"], "description": "RSB may use return predictions from outside the RSB" },
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"l1dflush_no": { "type": ["boolean", "null"], "description": "Not susceptible to L1D flush side-channel" },
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"ssb_no": { "type": ["boolean", "null"], "description": "Not susceptible to Speculative Store Bypass" },
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"mds_no": { "type": ["boolean", "null"], "description": "Not susceptible to MDS" },
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"taa_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSX Asynchronous Abort" },
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"pschange_msc_no": { "type": ["boolean", "null"], "description": "Page-size-change MSC not susceptible" },
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"tsx_ctrl_msr": { "type": ["boolean", "null"], "description": "TSX_CTRL MSR is present" },
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"tsx_ctrl_rtm_disable": { "type": ["boolean", "null"], "description": "RTM disabled via TSX_CTRL" },
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"tsx_ctrl_cpuid_clear": { "type": ["boolean", "null"], "description": "CPUID HLE/RTM bits cleared via TSX_CTRL" },
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"gds_ctrl": { "type": ["boolean", "null"], "description": "GDS_CTRL MSR present" },
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"gds_no": { "type": ["boolean", "null"], "description": "Not susceptible to Gather Data Sampling" },
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"gds_mitg_dis": { "type": ["boolean", "null"], "description": "GDS mitigation disabled" },
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"gds_mitg_lock": { "type": ["boolean", "null"], "description": "GDS mitigation locked" },
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"rfds_no": { "type": ["boolean", "null"], "description": "Not susceptible to Register File Data Sampling" },
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"rfds_clear": { "type": ["boolean", "null"], "description": "VERW clears register file stale data" },
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"its_no": { "type": ["boolean", "null"], "description": "Not susceptible to Indirect Target Selection" },
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"sbdr_ssdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to SBDR/SSDP" },
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"fbsdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to FBSDP" },
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"psdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to PSDP" },
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"fb_clear": { "type": ["boolean", "null"], "description": "Fill buffer cleared on idle/C6" },
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"rtm": { "type": ["boolean", "null"], "description": "Restricted Transactional Memory (TSX RTM) present" },
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"tsx_force_abort": { "type": ["boolean", "null"], "description": "TSX_FORCE_ABORT MSR present" },
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"tsx_force_abort_rtm_disable": { "type": ["boolean", "null"], "description": "RTM disabled via TSX_FORCE_ABORT" },
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"tsx_force_abort_cpuid_clear": { "type": ["boolean", "null"], "description": "CPUID RTM cleared via TSX_FORCE_ABORT" },
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"sgx": { "type": ["boolean", "null"], "description": "Software Guard Extensions present" },
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"srbds": { "type": ["boolean", "null"], "description": "SRBDS affected" },
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"srbds_on": { "type": ["boolean", "null"], "description": "SRBDS mitigation active" },
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"amd_ssb_no": { "type": ["boolean", "null"], "description": "AMD: not susceptible to Speculative Store Bypass" },
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"hygon_ssb_no": { "type": ["boolean", "null"], "description": "Hygon: not susceptible to Speculative Store Bypass" },
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"ipred": { "type": ["boolean", "null"], "description": "Indirect Predictor Barrier support" },
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"rrsba": { "type": ["boolean", "null"], "description": "Restricted RSB Alternate (Intel Retbleed mitigation)" },
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"bhi": { "type": ["boolean", "null"], "description": "Branch History Injection mitigation support" },
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"tsa_sq_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSA-SQ" },
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"tsa_l1_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSA-L1" },
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"verw_clear": { "type": ["boolean", "null"], "description": "VERW clears CPU buffers" },
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"autoibrs": { "type": ["boolean", "null"], "description": "AMD AutoIBRS (equivalent to enhanced IBRS on Intel)" },
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"sbpb": { "type": ["boolean", "null"], "description": "Selective Branch Predictor Barrier (AMD Inception mitigation)" },
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"avx2": { "type": ["boolean", "null"], "description": "AVX2 supported (relevant to Downfall / GDS)" },
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"avx512": { "type": ["boolean", "null"], "description": "AVX-512 supported (relevant to Downfall / GDS)" }
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"arch": { "type": "string", "const": "x86" },
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"vendor": {
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"description": "CPU vendor string: 'GenuineIntel', 'AuthenticAMD', or 'HygonGenuine'.",
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"type": ["string", "null"]
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},
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"friendly_name": {
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"description": "Human-readable CPU model from /proc/cpuinfo, e.g. 'Intel(R) Core(TM) i7-9700K CPU @ 3.60GHz'.",
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"type": ["string", "null"]
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},
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"x86": {
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"type": "object",
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"required": ["family", "model", "stepping", "cpuid", "platform_id", "hybrid", "codename", "capabilities"],
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"additionalProperties": false,
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"properties": {
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"family": {
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"description": "CPU family number.",
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"type": ["integer", "null"]
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},
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"model": {
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"description": "CPU model number.",
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"type": ["integer", "null"]
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},
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"stepping": {
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"description": "CPU stepping number.",
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"type": ["integer", "null"]
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},
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"cpuid": {
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"description": "Full CPUID leaf 1 EAX value as a hex string, e.g. '0x000906ed'.",
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"type": ["string", "null"],
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"pattern": "^0x[0-9a-f]+$"
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},
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"platform_id": {
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"description": "Intel platform ID from MSR 0x17. Null on AMD.",
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"type": ["integer", "null"]
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},
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"hybrid": {
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"description": "Whether this is a hybrid CPU (P-cores + E-cores, e.g. Alder Lake). Null if undeterminable.",
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"type": ["boolean", "null"]
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},
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"codename": {
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"description": "Intel CPU codename, e.g. 'Coffee Lake'. Null on AMD.",
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"type": ["string", "null"]
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},
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"capabilities": {
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"description": "CPU feature flags detected via CPUID and MSR reads. Each value is true (present), false (absent), or null (not applicable or could not be read).",
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"type": "object",
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"additionalProperties": false,
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"properties": {
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"spec_ctrl": { "type": ["boolean", "null"], "description": "SPEC_CTRL MSR present (Intel; enables IBRS + IBPB via WRMSR)" },
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"ibrs": { "type": ["boolean", "null"], "description": "Indirect Branch Restricted Speculation" },
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"ibpb": { "type": ["boolean", "null"], "description": "Indirect Branch Prediction Barrier" },
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"ibpb_ret": { "type": ["boolean", "null"], "description": "IBPB on return (enhanced form)" },
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"stibp": { "type": ["boolean", "null"], "description": "Single Thread Indirect Branch Predictors" },
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"ssbd": { "type": ["boolean", "null"], "description": "Speculative Store Bypass Disable" },
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"l1d_flush": { "type": ["boolean", "null"], "description": "L1D cache flush instruction" },
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"md_clear": { "type": ["boolean", "null"], "description": "VERW clears CPU buffers (MDS mitigation)" },
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"arch_capabilities": { "type": ["boolean", "null"], "description": "IA32_ARCH_CAPABILITIES MSR is present" },
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"rdcl_no": { "type": ["boolean", "null"], "description": "Not susceptible to RDCL (Meltdown-like attacks)" },
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"ibrs_all": { "type": ["boolean", "null"], "description": "Enhanced IBRS always-on mode supported" },
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"rsba": { "type": ["boolean", "null"], "description": "RSB may use return predictions from outside the RSB" },
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"l1dflush_no": { "type": ["boolean", "null"], "description": "Not susceptible to L1D flush side-channel" },
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"ssb_no": { "type": ["boolean", "null"], "description": "Not susceptible to Speculative Store Bypass" },
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"mds_no": { "type": ["boolean", "null"], "description": "Not susceptible to MDS" },
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"taa_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSX Asynchronous Abort" },
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"pschange_msc_no": { "type": ["boolean", "null"], "description": "Page-size-change MSC not susceptible" },
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"tsx_ctrl_msr": { "type": ["boolean", "null"], "description": "TSX_CTRL MSR is present" },
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"tsx_ctrl_rtm_disable": { "type": ["boolean", "null"], "description": "RTM disabled via TSX_CTRL" },
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"tsx_ctrl_cpuid_clear": { "type": ["boolean", "null"], "description": "CPUID HLE/RTM bits cleared via TSX_CTRL" },
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"gds_ctrl": { "type": ["boolean", "null"], "description": "GDS_CTRL MSR present" },
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"gds_no": { "type": ["boolean", "null"], "description": "Not susceptible to Gather Data Sampling" },
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"gds_mitg_dis": { "type": ["boolean", "null"], "description": "GDS mitigation disabled" },
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"gds_mitg_lock": { "type": ["boolean", "null"], "description": "GDS mitigation locked" },
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"rfds_no": { "type": ["boolean", "null"], "description": "Not susceptible to Register File Data Sampling" },
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"rfds_clear": { "type": ["boolean", "null"], "description": "VERW clears register file stale data" },
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"its_no": { "type": ["boolean", "null"], "description": "Not susceptible to Indirect Target Selection" },
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"sbdr_ssdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to SBDR/SSDP" },
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"fbsdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to FBSDP" },
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"psdp_no": { "type": ["boolean", "null"], "description": "Not susceptible to PSDP" },
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"fb_clear": { "type": ["boolean", "null"], "description": "Fill buffer cleared on idle/C6" },
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"rtm": { "type": ["boolean", "null"], "description": "Restricted Transactional Memory (TSX RTM) present" },
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"tsx_force_abort": { "type": ["boolean", "null"], "description": "TSX_FORCE_ABORT MSR present" },
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"tsx_force_abort_rtm_disable": { "type": ["boolean", "null"], "description": "RTM disabled via TSX_FORCE_ABORT" },
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"tsx_force_abort_cpuid_clear": { "type": ["boolean", "null"], "description": "CPUID RTM cleared via TSX_FORCE_ABORT" },
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"sgx": { "type": ["boolean", "null"], "description": "Software Guard Extensions present" },
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"srbds": { "type": ["boolean", "null"], "description": "SRBDS affected" },
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"srbds_on": { "type": ["boolean", "null"], "description": "SRBDS mitigation active" },
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"amd_ssb_no": { "type": ["boolean", "null"], "description": "AMD: not susceptible to Speculative Store Bypass" },
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"hygon_ssb_no": { "type": ["boolean", "null"], "description": "Hygon: not susceptible to Speculative Store Bypass" },
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"ipred": { "type": ["boolean", "null"], "description": "Indirect Predictor Barrier support" },
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"rrsba": { "type": ["boolean", "null"], "description": "Restricted RSB Alternate (Intel Retbleed mitigation)" },
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"bhi": { "type": ["boolean", "null"], "description": "Branch History Injection mitigation support" },
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"tsa_sq_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSA-SQ" },
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"tsa_l1_no": { "type": ["boolean", "null"], "description": "Not susceptible to TSA-L1" },
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"verw_clear": { "type": ["boolean", "null"], "description": "VERW clears CPU buffers" },
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"autoibrs": { "type": ["boolean", "null"], "description": "AMD AutoIBRS (equivalent to enhanced IBRS on Intel)" },
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"sbpb": { "type": ["boolean", "null"], "description": "Selective Branch Predictor Barrier (AMD Inception mitigation)" },
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"avx2": { "type": ["boolean", "null"], "description": "AVX2 supported (relevant to Downfall / GDS)" },
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"avx512": { "type": ["boolean", "null"], "description": "AVX-512 supported (relevant to Downfall / GDS)" }
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}
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}
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}
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}
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}
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},
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{
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"type": "object",
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"description": "ARM CPU (ARM, Cavium, Phytium).",
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"required": ["arch", "vendor", "friendly_name", "arm"],
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"additionalProperties": false,
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"properties": {
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"arch": { "type": "string", "const": "arm" },
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"vendor": {
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"description": "CPU vendor string: 'ARM', 'CAVIUM', or 'PHYTIUM'.",
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"type": ["string", "null"]
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},
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"friendly_name": {
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"description": "Human-readable CPU model, e.g. 'ARM v8 model 0xd0b'.",
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"type": ["string", "null"]
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},
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"arm": {
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"type": "object",
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"required": ["part_list", "arch_list", "capabilities"],
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"additionalProperties": false,
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"properties": {
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"part_list": {
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"description": "Space-separated list of ARM part numbers detected across cores, e.g. '0xd0b 0xd05' (big.LITTLE).",
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"type": ["string", "null"]
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},
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"arch_list": {
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"description": "Space-separated list of ARM architecture levels detected across cores, e.g. '8 8'.",
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"type": ["string", "null"]
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},
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"capabilities": {
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"description": "ARM-specific CPU capability flags. Currently empty; reserved for future use.",
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"type": "object",
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"additionalProperties": false,
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"properties": {}
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}
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}
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}
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}
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}
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}
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]
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},
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"cpu_microcode": {
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